The invention discloses a low power scan testing method and device based on sequential equal segmentation. The method includes 1, allowing the lengths of parallax executed scan chains to be equal by balancing the lengths of scan chains; applying one segmentation enable signal to each scan chain, and segmenting the scan chains into short ones sequentially and equally; 2, when the scan chains execute scan tests parallax, in a scan movement mode, scanning in a segmentation mode under the control of the segmentation enable signals, and allowing the short scan chains to move in a segmented manner; when the clock period when the test excitation cannot be multiplexed is executed, controlling the short scans chain to recover to the original scan chains before segmentation for long chain mode scanning through the segmentation enable signals. The device comprises a balancing and segmenting module and a testing control module. The method has the advantages of simpleness and low power; the method is adaptive to scan tests of multiple parallel scan chains, and the test movement is accurate.

Low power scan testing method and device based on sequential equal segmentation

This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35% on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58% to 11%.

FPGA interconnect timing library based on the statistical method

This paper presents a completely unified interconnect unit (UINT) including unified input and output multiplexers (UIM and UOM) which are usually non-repeatable [1–3]. UINT ensures different logic modules could have exactly the identical interconnect circuit, providing higher scalability for FPGAs. Furthermore, Multi-Vt switch circuit combining low threshold voltage and high threshold voltage transistors is put forward to minimize the adverse effects brought by threshold voltage loss and decrease of Supply Voltage in Nanometer technology, attaining high speed performance of FPGA. The proposed interconnect unit is applied to own-designed Fudan Programmable (FDP5) FPGA and realized through 65nm technology. Post-layout simulation results indicate that the proposed interconnect circuit is well-designed with up to 40% improvement of speed performance compared to the prior work [3] equivalent to the same technology, yet maintaining lower power consumption and smaller area, reduced by 12% and 35% respectively.

Improved unified interconnect unit for high speed and scalable FPGA

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

https://iopscience.iop.org/article/10.1088/1674-4926/32/5/055012/pdf

A new FPGA architecture suitable for DSP applications

The invention provides an element-based closed-loop test method. Element configuration is performed through configuration software, the output of each element acts as the input of the next element, and the obtained output of the next element is enabled to be the input of the last element through the reverse configuration algorithm of the last element until the output of the final element is given to the input of the first element so as to form the logic configuration of a closed loop for testing. According to the closed-loop test method, the performing correctness of the elements can be visually seen so that operation is easy and the efficiency is high.

Element-based closed-loop test method

The invention relates to a scanning chain circuit for an FPGA (Field Programmable Gate Array) interpolating and interconnecting test, belonging to the FPGA technical field. By using triggers of programmable logic parts in a chip, the programmable logic parts of an FPGA are mutually serially connected to form a scanning chain which is specially used for testing an interconnecting wire and controlled by using a scanning mode signal; meanwhile, according to the requirements, the scanning chain is segmented into a plurality of sections by using IO to improve the flexibility of the scanning chain. Because of multiplexing the triggers, the area added because of inserting the scanning chain is very little, and the difficulty of the interconnecting test can be greatly reduced.

Scanning chain circuit for FPGA (Field Programmable Gate Array) interpolating and interconnecting test

A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our idea1.

Uniform routing architecture for FPGA with embedded IP cores

A uniform routing architecture is presented, which offers CLB, lOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our ideal.

http://ieeexplore.ieee.org/iel5/5341889/5351163/05351594.pdf

Xing Chen

Papers

Scanning chain circuit for FPGA (Field Programmable Gate Array) interpolating and interconnecting test

Uniform routing architecture for FPGA with embedded IP cores

Uniform Routing Architecture for FPGAwith