The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

Static-noise margin analysis of MOS SRAM cells

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.

A Self-Testing Dynamic RAM Chip

A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

Alpha-particle-induced soft error rates (SERs) in RAMs were measured by exposing commercial chips, with lid and protective coating removed, to an Americium-241 alpha source. These measurements have shown that, under normal operating conditions, resistive load SRAMs can be as sensitive as DRAMs. Measurements of variations of SER with cycle time and supply voltage were in broad agreement with a model previously suggested by other workers, and explanations are proposed for the different regions of operation. The effect of an alpha-particle hit on SRAM cell is simulated using SPICE with typical process parameters. A simple analysis of the model highlights the features that determine the critical charge. The behavior predicted by this model is different in a small but significant way from that predicted by previous workers: it was confirmed by SPICE simulation. Various parameters in the cell model were changed in order to investigate the effects on the alpha-particle sensitivity, and the results of these simulations suggest a mechanism by which the sensitivity could most economically be improved. By combining the result of the simulations and experiments, quantitative estimates of expected SER improvements are presented.

Influences on soft error rates in static RAMs

Describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a DC stability factor introduced from transfer curves of the inverters in the cell. The criteria use only static conditions for read/write/retain operations. The designed cell, considering mask-misalignment, measured 22.8/spl times/27.6 /spl mu/m with 2.5 /spl mu/m layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

Design consideration of a static memory cell

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

Y. Hirata

Papers

Design consideration of a static memory cell

A 35 ns 16K NMOS static RAM

Parasitic Resistance Effects on Static MOS RAM