The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

Static-noise margin analysis of MOS SRAM cells

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations.
We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space.
Our DPGA, a fine-grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite-state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds.
Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20$\times$ the computational density of conventional processors.
Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Reconfigurable Architectures for General-Purpose Computing

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

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On the Design of

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

Describes a self-learning neural network chip with refresh on-chip analog synaptic weight storage. The chip integrates 400 neurons and 40000 synapses with 0.8- mu m double poly-Si double metal CMOS technology. Refresh time is less than 300 mu s. The chip retains learned information by repeating refresh at 100 ms intervals. The proposed refresh method is based on the decision made by a subnetwork. The subnetwork learns if the settling states of the main network should be memorized, retains the weights until they are relearned, and stores a 4-b representation of subnetwork weights in a counter. The main network is refreshed according to the output of the subnetwork. >

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses

Describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a DC stability factor introduced from transfer curves of the inverters in the cell. The criteria use only static conditions for read/write/retain operations. The designed cell, considering mask-misalignment, measured 22.8/spl times/27.6 /spl mu/m with 2.5 /spl mu/m layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

Design consideration of a static memory cell

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-/spl mu/m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 /spl mu/s.

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

http://ieeexplore.ieee.org/iel6/8303/25935/01157108.pdf

H. Shinohara

Papers

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses

Design consideration of a static memory cell

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

A 34ns 1Mb CMOS SRAM using triple poly