In this paper, various fault location techniques in analog networks are described and compared. The emphasis is on the more recent developments in the subject. Four main approaches for fault location are addressed, examined, and illustrated using simple network examples. In particular, we consider the fault dictionary approach, the parameter identification approach, the fault verification approach, and the approximation approach. Theory and algorithms that are associated with these approaches are reviewed and problems of their practical application are identified. Associated with the fault dictionary approach we consider fault dictionary construction techniques, methods of optimum measurement selection, different fault isolation criteria, and efficient fault simulation techniques. Parameter identification techniques that either utilize linear or nonlinear systems of equations to identify all network elements are examined very thoroughly. Under fault verification techniques we discuss node-fault diagnosis, branch-fault diagnosis, subnetwork testability conditions as well as combinatorial techniques, the failure bound technique, and the network decomposition technique. For the approximation approach we consider probabilistic methods and optimization-based methods. The artificial intelligence technique and the different measures of testability are also considered. The main features of the techniques considered are summarized in a comparative table. An extensive, but not exhaustive, bibliography is provided.

Fault diagnosis of analog circuits

We study the problem of finding ground states of spin glasses with exterior magnetic field, and the problem of minimizing the number of vias holes on a printed circuit board, or contacts on a chip subject to pin preassignments and layer preferences. The former problem comes up in solid-state physics, and the latter in very-large-scale-integrated VLSI circuit design and in printed circuit board design. Both problems can be reduced to the max-cut problem in graphs. Based on a partial characterization of the cut polytope, we design a cutting plane algorithm and report on computational experience with it. Our method has been used to solve max-cut problems on graphs with up to 1,600 nodes.

An application of combinatorial optimization to statistical physics and circuit layout design

The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

Given an undirected graph with edge weights, the MAX-CUT problem consists in finding a partition of the nodes into two subsets, such that the sum of the weights of the edges having endpoints in different subsets is maximized. It is a well-known NP-hard problem with applications in several fields, including VLSI design and statistical physics. In this article, a greedy randomized adaptive search procedure (GRASP), a variable neighborhood search (VNS), and a path-relinking (PR) intensification heuristic for MAX-CUT are proposed and tested. New hybrid heuristics that combine GRASP, VNS, and PR are also proposed and tested. Computational results indicate that these randomized heuristics find near-optimal solutions. On a set of standard test problems, new best known solutions were produced for many of the instances.

http://www.optimization-online.org/DB_FILE/2002/06/497.pdf

Randomized heuristics for the max-cut problem

Mathematical Preliminaries Sets Vectors and matrices Linear inequality systems Graphs Graphs: basic notions Graphs and vector spaces Basic operations on graphs and vector spaces Problems Graph algorithms Duality Notes Matroids Axiom systems for matroids Dual of a matroid Minors of matroids Connectedness in matroids Matroids and the greedy algorithm Notes Electrical Networks In terms of multiterminal devices In terms of 2-terminal devices Standard devices Common methods of analysis Procedures used in circuit simulators State equations for dynamic networks Multiports in electrical networks Some elementary results of network theory Notes Topological Hybrid Analysis Electrical network: a formal description Some basic topological results A theorem on topological hybrid analysis Structure of constraints and optimization Notes The Implicit Duality Theorem and its Applications The vector space version *Quasi orthogonality Applications of the implicit duality theorem *Linear inequality systems *ast Integrality systems Problems Notes Multiport Decomposition Multiport decomposition of vector spaces Analysis through multiport decomposition Port minimization * Multiport decomposition for network reduction Problems Submodular Functions Submodularity Basic operations on semimodular functions *Other operations on semimodular functions Polymatroid and matroid rank functions Connectedness for semimodular functions *Semimodular polyhedra Symmetric submodular functions Problems Notes Convolution of Submodular Functions Convolution Matroids, polymatroids and convolution The principal partition *The refined partial order of the principal partition Algorithms for PP *Aligned polymatroid rank functions Notes Matroid Union Submodular functions induced through a bipartite graph Matroid union: algorithm and structure PP of the rank function of a matroid Notes Dilworth Truncation of Submodular Functions Dilworth truncation The principal lattice of partitions *Approximation algorithms through PLP for the min cost partition problem The PLP of duals and truncations *The principal lattice of partitions associated with special fusions Building submodular functions with desired PLP Notes Algorithms for the PLP of a Submodular Function Minimizing the partition associate of a submodular function Construction of the P-sequence of partitions Construction of the DTL Complexity of construction of the PLP Construction of the PLP of the dual PLP algorithms for (omega R Gamma) and -(omega R Epsilon L ) Structural changes in minimizing partitions Relation between PP and PLP Fast algorithms for principal partition of the rank function of a graph The Hybrid Rank Problem The hybrid rank problem - first formulation The hybrid rank problem - second formulation The hybrid rank problem - third formulation The hybrid rank problem - fourth formulation

Submodular functions and electrical networks

Based on graph theory, an efficient via minimization algorithm for certain types of two-layer printed circuit boards is developed which can be executed in polynomial time. The algorithm yields solutions for routings with junctions of degrees varying from 2 to 8 and guarantees the minimum number of vias for routings with three or fewer line segments connected to each junction. Examples are given to illustrate various aspects of the algorithm. In addition, preassignment of line segments on a particular layer of the board due to certain prescribed board (or component) constraints is discussed.

A graph-theoretic via minimization algorithm for two-layer printed circuit boards

The problem of diagnosis studied here is to determine the currents and/or voltages of desired elements from the measured currents and/or voltages of certain other elements. A necessary and sufficient condition for diagnosablity is given in connection with the structure of 2-graphs. The relationship between the structure and the electrical connectivity is presented to show the diagnosability depends on the connectivity of the network. In diagnosis of a large network it may often happen that only a part of the currents and voltages in the whole network need be solved. Some condition for this partial solvability is given.

Y. Kajitani

Papers

A graph-theoretic via minimization algorithm for two-layer printed circuit boards

Diagnosability of linear active networks