The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Sigma 2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3- mu m CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm/sup 2/, and has achieved a measured dynamic range of 89 dB. >

The design of sigma-delta modulation analog-to-digital converters

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

A higher order topology for interpolative modulators for oversampling A/D converters

The jitter of such practical sampling systems as analog-to-digital converters, sample-and-hold circuits, and samplers is discussed. A model for estimating jitter is proposed. In this model, total jitter is composed of sampling circuit jitter, analog input signal jitter, and sampling clock jitter. Using this model, jitter is broken up into three components. To evaluate the model, a precise method for measuring jitter is devised. This method, based on sampling sine-wave signal-to-noise ratio calculations, enables separation of jitter and amplitude noise. The performance limit of converters as evaluated by the model is discussed. >

Jitter analysis of high-speed sampling systems

A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3- mu m CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate. >

A noise-shaping coder topology for 15+ bit converters

A highly stable triple-integration noise-shaping technology which permits greater accuracy for monolithic audio A/D converters is discussed. Based on this technology, a 16-bit 24-kHz bandwidth A-D converter LSI with digital filters was successfully fabricated in 2-/spl mu/m CMOS technology. An SNR (S/(N+THD)) of 91 dB and a total harmonic distortion (THD) of 0.002% at full-scale input were attained.

/pdf/a-16-bit-oversampling-a-to-d-conversion-technology-using-4nzmp67uvp.pdf

A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping

A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5 mu m CMOS technology, a 17 bit 20 kHz bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N+THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained. >

/pdf/a-17-bit-oversampling-d-a-conversion-technology-using-sd7m6ngwc5.pdf

Y. Matsuya

Papers

A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping

A 17 bit oversampling D-A conversion technology using multistage noise shaping