Showing papers by "Yan Lin published in 2006"

Ethanol fermentation from biomass resources: current state and prospects.

Abstract: In recent years, growing attention has been devoted to the conversion of biomass into fuel ethanol, considered the cleanest liquid fuel alternative to fossil fuels. Significant advances have been made towards the technology of ethanol fermentation. This review provides practical examples and gives a broad overview of the current status of ethanol fermentation including biomass resources, microorganisms, and technology. Also, the promising prospects of ethanol fermentation are especially introduced. The prospects included are fermentation technology converting xylose to ethanol, cellulase enzyme utilized in the hydrolysis of lignocellulosic materials, immobilization of the microorganism in large systems, simultaneous saccharification and fermentation, and sugar conversion into ethanol.

Placement and Timing for FPGAs Considering Variations

Abstract: Process variation affecting timing and power is an important issue for modem integrated circuits in nanometer technologies. FPGAs are similar to ASICs in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. This paper presents the first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs. Considering the uniqueness of re-programmability in FPGAs, we quantify the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield. We also develop a new variation aware placement, which is the first statistical algorithm for FPGA layout and reduces yield loss by 3.4X with guard-banding and 25X with speed-binning for MCNC and QUIP designs.

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction

Abstract: Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dual-Vdd for given time slack. In this paper, we show that such lower bound estimation cannot be extended to mixed length interconnects that are used in modern FPGAs. We develop a technique to estimate power reduction using dual-Vdd for mixed length interconnects, and apply linear programming (LP) to solve slack budgeting to minimize power for mixed length interconnects. Experiments show 53% power reduction on average compared to single-Vdd interconnects. Furthermore, this paper presents a simultaneous retiming and slack budgeting algorithm to reduce power in dual-Vdd FPGAs considering placement and flip-flop binding constraints. The algorithm is based on mixed integer and linear programming (MILP) and achieves up to 20% power reduction compared to retiming followed by slack budgeting. We propose a runtime efficient flow to apply simultaneous retiming and slack budgeting only when it is necessary. To the best of our knowledge, this paper is the first; in-depth study of simultaneous retiming and slack budgeting for dual-Vdd programmable FPGA power reduction while considering layout constraints.

Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction

Abstract: To reduce field-programmable gate array power, Vdd programmability has been recently proposed to select the Vdd level for interconnects and power-gate unused interconnects. However, Vdd-level converters used in the existing Vdd-programmable method consume a large amount of leakage. This paper proposes two ways to avoid using level converters in interconnects, namely; 1) tree-based level converter insertion (TLC) and 2) dual-Vdd tree-based level converter insertion (dTLC). TLC enforces that there is only one Vdd level within each routing tree, while dTLC can have different Vdd levels within a routing tree, but no VddL switch drives VddH switches. Dual-Vdd assignment algorithms were developed considering chip-level time slack allocation for maximum power reduction. The algorithms include TLC-S and dTLC-S, two power sensitivity-based algorithms with implicit time slack allocation, and dTLC-LP, a linear programming (LP)-based algorithm with explicit time slack allocation. All allocate time slack first to interconnects with higher power sensitivity and assign low Vdd to them for more power reduction. Experiments show that dTLC-LP obtains the lowest power consumption. Compared to dTLC-LP, dTLC-S obtains a slightly higher power consumption but runs three times faster. Compared to the existing segment-based level converter insertion for dual Vdd, dTLC-LP reduces interconnect power by 52.90% without performance loss for Microelectronics Center of North Carolina benchmark circuits

Characterization of a Newly Isolated Heterotrophic Nitrifying Bacterium

Abstract: Continuous experiments were performed in a membrane bioreactor (MBR) system. Under the tested conditions, 49.4 to 90.6% of total nitrogen (TN) was found to be removed. The COD/TN ratio as well as the dissolved oxygen (DO) concentration was the key factor influencing the TN removal efficiency. A heterotrophic nitrifier, named Bacillus sp. LY , was newly isolated from the system. Batch experiments show that Bacillus sp. LY could utilize the organic carbon as the source of assimilation when it grew on glucose and ammonium chloride medium accompanying the formation of oxidized-nitrogen. It also could denitrify nitrate while nitrification. After 24 days incubation, the removal efficiencies of the COD and TN by Bacillus sp. LY were 71.7% and 61.2%, respectively. The phylogenetic analysis of Bacillus sp. LY was performed and the phylogenetic tree of Bacillus sp. LY and the neighboring nitrifiers was given.

Isolation of a new heterotrophic nitrifying Bacillus sp. strain.

Abstract: A heterotrophic nitrifier, named Bacillus sp. LY, was newly isolated from a membrane bioreactor (MBR). Bacillus sp. LY could utilize the organic carbon as the source of assimilation when it grew on glucose and ammonium chloride medium companying the formation of oxidized-nitrogen. It also could denitrify nitrate while nitrification. After 24 days incubation, the removal efficiencies of the COD and TN by Bacillus sp. LY were 71.7% and 61.2%, respectively. The phylogenetic analysis of Bacillus sp. LY was performed and the phylogenetic tree of Bacillus sp. LY and the neighbouring nitrifiers was given. Bacillus sp. LY could become a new bacterial resource for heterotrophic nitrification and might play a bioremediation role for nutrient removal.

Isolation and characterization of heterotrophic nitrifying bacteria

Abstract: Method of isolating the heterotrophic nitrifiers and the characterization of the heterotrophic nitrification were studied. Two heterotrophic nitrifiers were newly isolated from a membrane bioreactor (MBR) in which the TN removal efficiency was 80.1%. The batch test results indicate that Bacillus sp. LY and Brevibacillus sp. LY could utilize the organic carbon as the source of assimilation when they grew on glucose and ammonium chloride medium companying the formation of oxidized-nitrogen. After 24 days incubation, the removal efficiencies of the COD by Bacillus sp. LY and Brevibacillus sp. LY were 71.7% and 52.6%, respectively. The removal efficiencies of ammonium nitrogen by the two isolates were 78.2% and 51.2% and the TN removal efficiencies by the two isolates were 61.2% and 35.6%, respectively.

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction

Abstract: To reduce FPGA power, a linear programming (LP) based time slack allocation algorithm, EdTLC-LP, has been proposed recently for Vdd-programmable interconnects without using Vdd-level converters for mixed wire lengths. However, it takes a long time to solve the LP problem for time slack allocation. In this paper, we develop EdTLC-NW, a slack allocation algorithm based on min-cost network flow to reduce runtime. Compared to single Vdd FPGA with power-gating, EdTLC-LP and EdTLC-NW reduce interconnect power by 52.71% and 52.52%, respectively. EdTLC-NW achieves as good results as EdTLC-LP but runs 8times faster on average. Furthermore, the speedup increases for larger circuits and EdTLC-NW is 20times faster for the largest circuit