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Yanbin Luo
Researcher at Beijing University of Posts and Telecommunications
Publications - 21
Citations - 230
Yanbin Luo is an academic researcher from Beijing University of Posts and Telecommunications. The author has contributed to research in topics: Graphene & Nanowire. The author has an hindex of 7, co-authored 20 publications receiving 122 citations. Previous affiliations of Yanbin Luo include Nanjing University of Aeronautics and Astronautics.
Papers
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Journal ArticleDOI
A graphene/single GaAs nanowire Schottky junction photovoltaic device
Yanbin Luo,Xin Yan,Jinnan Zhang,Bang Li,Yao Wu,Qichao Lu,Chenxiaoshuai Jin,Xia Zhang,Xiaomin Ren +8 more
TL;DR: The graphene/single GaAs nanowire Schottky junction photovoltaic device demonstrated here is promising for self-powered high-speed photodetectors and low-cost high-efficiency solar cells.
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Graphene-Based Multi-Beam Reconfigurable THz Antennas
Yanbin Luo,Qingsheng Zeng,Xin Yan,Yong Wu,Qichao Lu,Chaofan Zheng,Nan Hu,Wenqing Xie,Xia Zhang +8 more
TL;DR: This paper provides an easy way to obtain complex graphene-based multi-beam antennas, showing strong potential in the design of other complex graphene -based systems, enabling nanoscale wireless communications and sensing devices for different applications.
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Mimicking synaptic functionality with an InAs nanowire phototransistor
Bang Li,Wei Wei,Wei Wei,Xin Yan,Xia Zhang,Peng Liu,Yanbin Luo,Jiahui Zheng,Qichao Lu,Qimin Lin,Xiaomin Ren +10 more
TL;DR: A nanowire (NW) phototransistor with synaptic behavior based on inherent persistent photoconductivity with promising applications in neuromorphic systems and networks is demonstrated.
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A graphene-based tunable negative refractive index metamaterial and its application in dynamic beam-tilting terahertz antenna
Yanbin Luo,Yanbin Luo,Qingsheng Zeng,Xin Yan,Tao Jiang,Rongcao Yang,Jiayun Wang,Yong Wu,Qichao Lu,Xia Zhang +9 more
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High-speed ultra-compact all-optical NOT and AND logic gates designed by a multi-objective particle swarm optimized method
Qichao Lu,Xin Yan,Wei Wei,Xia Zhang,Mingqian Zhang,Jiahui Zheng,Bang Li,Yanbin Luo,Qimin Lin,Xiaomin Ren +9 more
TL;DR: The design method could have tolerance for small changes in device geometry, which means that the logic gates could remain functional while the pixel side length ranges from 112 to 125 nm, which makes these devices promising for future photonic-integrated circuits.