This document provides updates to IEEE Std 802.16's MIB for the MAC, PHY and asso- ciated management procedures in order to accommodate recent extensions to the standard.

IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems Draft Amendment: Management Information Base Extensions

Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

/pdf/high-level-synthesis-for-fpgas-from-prototyping-to-4vlvkebjds.pdf

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Driven by the need to cope with exponentially growing mobile data traffic and to support new traffic types from massive numbers of machine-type devices, academia and industry are thinking beyond the current generation of mobile cellular networks to chalk a path towards fifth generation (5G) mobile networks. Several new approaches and technologies are being considered as potential elements making up such a future mobile network, including cloud RANs, application of SDN principles, exploiting new and unused portions of spectrum, use of massive MIMO and full-duplex communications. Research on these technologies requires realistic and flexible experimentation platforms that offer a wide range of experimentation modes from real-world experimentation to controlled and scalable evaluations while at the same time retaining backward compatibility with current generation systems. Towards this end, we present OpenAirInterface (OAI) as a suitably flexible platform. In addition, we discuss the use of OAI in the context of several widely mentioned 5G research directions.

/pdf/openairinterface-a-flexible-platform-for-5g-research-2sc2xt49j2.pdf

OpenAirInterface: A Flexible Platform for 5G Research

Spectrum decision is the ability of a cognitive radio (CR) to select the best available spectrum band to satisfy secondary users' (SUs') quality of service (QoS) requirements, without causing harmful interference to licensed or primary users (PUs). Each CR performs spectrum sensing to identify the available spectrum bands and the spectrum decision process selects from these available bands for opportunistic use. Spectrum decision constitutes an important topic which has not been adequately explored in CR research. Spectrum decision involves spectrum characterization, spectrum selection and CR reconfiguration functions. After the available spectrum has been identified, the first step is to characterize it based not only on the current radio environment conditions, but also on the PU activities. The second step involves spectrum selection, whereby the most appropriate spectrum band is selected to satisfy SUs' QoS requirements. Finally, the CR should be able to reconfigure its transmission parameters to allow communication on the selected band. Key to spectrum characterization is PU activity modelling, which is commonly based on historical data to provide the means for predicting future traffic patterns in a given spectrum band. This paper provides an up-to-date survey of spectrum decision in CR networks (CRNs) and addresses issues of spectrum characterization (including PU activity modelling), spectrum selection and CR reconfiguration. For each of these issues, we highlight key open research challenges. We also review practical implementations of spectrum decision in several CR platforms.

/pdf/spectrum-decision-in-cognitive-radio-networks-a-survey-4zyh1oas7j.pdf

Spectrum Decision in Cognitive Radio Networks: A Survey

Widely regarded as one of the most promising emerging technologies for driving the future development of wireless communications, cognitive radio has the potential to mitigate the problem of increasing radio spectrum scarcity through dynamic spectrum allocation. Drawing on fundamental elements of information theory, network theory, propagation, optimisation and signal processing, a team of leading experts present a systematic treatment of the core physical and networking principles of cognitive radio and explore key design considerations for the development of new cognitive radio systems. Containing all the underlying principles you need to develop practical applications in cognitive radio, this book is an essential reference for students, researchers and practitioners alike in the field of wireless communications and signal processing.

/pdf/principles-of-cognitive-radio-2cmaz71gzs.pdf

Principles Of Cognitive Radio

https://www.ece.rice.edu/~ys4937/distribute/2011-Integration-Turbo.pdf

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

In this paper, we introduce the wireless open-access research platform (WARP) developed at CMC lab, Rice University. WARP provides a scalable and configurable platform mainly designed to prototype wireless communication algorithms for educational and research oriented applications. Its programmability and flexibility makes it easy to implement various physical and network layer protocols and standards. Moreover, the online open-access WARP repository is used to document and share different wireless architectures and cross-layer designs developed at educational and research centers. This repository is a fast and easy solution for students and researchers with a wide range of backgrounds in hardware implementation and algorithm development to collaborate and initiate multi-disciplinary system designs.

/pdf/warp-a-unified-wireless-network-testbed-for-education-and-5gtfoq6mmy.pdf

WARP, a Unified Wireless Network Testbed for Education and Research

A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multi-rate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between frac14 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.

/pdf/vlsi-decoder-architecture-for-high-throughput-variable-block-4oyvo42zaq.pdf

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.

/pdf/configurable-and-scalable-high-throughput-turbo-decoder-40n6zciliy.pdf

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapath and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Min-sum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient soft-input soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC 90 nm 1.0 V 8-metal layer CMOS technology with a total area of 3.5 mm2. The maximum clock frequency is 450 MHz and the estimated peak power consumption is 410 mW.

/pdf/a-low-power-1-gbps-reconfigurable-ldpc-decoder-design-for-1i27qjq1df.pdf

Yang Sun

Papers

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

WARP, a Unified Wireless Network Testbed for Education and Research

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards