This document provides updates to IEEE Std 802.16's MIB for the MAC, PHY and asso- ciated management procedures in order to accommodate recent extensions to the standard.

IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems Draft Amendment: Management Information Base Extensions

Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

/pdf/high-level-synthesis-for-fpgas-from-prototyping-to-4vlvkebjds.pdf

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Driven by the need to cope with exponentially growing mobile data traffic and to support new traffic types from massive numbers of machine-type devices, academia and industry are thinking beyond the current generation of mobile cellular networks to chalk a path towards fifth generation (5G) mobile networks. Several new approaches and technologies are being considered as potential elements making up such a future mobile network, including cloud RANs, application of SDN principles, exploiting new and unused portions of spectrum, use of massive MIMO and full-duplex communications. Research on these technologies requires realistic and flexible experimentation platforms that offer a wide range of experimentation modes from real-world experimentation to controlled and scalable evaluations while at the same time retaining backward compatibility with current generation systems. Towards this end, we present OpenAirInterface (OAI) as a suitably flexible platform. In addition, we discuss the use of OAI in the context of several widely mentioned 5G research directions.

/pdf/openairinterface-a-flexible-platform-for-5g-research-2sc2xt49j2.pdf

OpenAirInterface: A Flexible Platform for 5G Research

Spectrum decision is the ability of a cognitive radio (CR) to select the best available spectrum band to satisfy secondary users' (SUs') quality of service (QoS) requirements, without causing harmful interference to licensed or primary users (PUs). Each CR performs spectrum sensing to identify the available spectrum bands and the spectrum decision process selects from these available bands for opportunistic use. Spectrum decision constitutes an important topic which has not been adequately explored in CR research. Spectrum decision involves spectrum characterization, spectrum selection and CR reconfiguration functions. After the available spectrum has been identified, the first step is to characterize it based not only on the current radio environment conditions, but also on the PU activities. The second step involves spectrum selection, whereby the most appropriate spectrum band is selected to satisfy SUs' QoS requirements. Finally, the CR should be able to reconfigure its transmission parameters to allow communication on the selected band. Key to spectrum characterization is PU activity modelling, which is commonly based on historical data to provide the means for predicting future traffic patterns in a given spectrum band. This paper provides an up-to-date survey of spectrum decision in CR networks (CRNs) and addresses issues of spectrum characterization (including PU activity modelling), spectrum selection and CR reconfiguration. For each of these issues, we highlight key open research challenges. We also review practical implementations of spectrum decision in several CR platforms.

/pdf/spectrum-decision-in-cognitive-radio-networks-a-survey-4zyh1oas7j.pdf

Spectrum Decision in Cognitive Radio Networks: A Survey

Widely regarded as one of the most promising emerging technologies for driving the future development of wireless communications, cognitive radio has the potential to mitigate the problem of increasing radio spectrum scarcity through dynamic spectrum allocation. Drawing on fundamental elements of information theory, network theory, propagation, optimisation and signal processing, a team of leading experts present a systematic treatment of the core physical and networking principles of cognitive radio and explore key design considerations for the development of new cognitive radio systems. Containing all the underlying principles you need to develop practical applications in cognitive radio, this book is an essential reference for students, researchers and practitioners alike in the field of wireless communications and signal processing.

/pdf/principles-of-cognitive-radio-2cmaz71gzs.pdf

Principles Of Cognitive Radio

This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential un-timed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW.

/pdf/scalable-and-low-power-ldpc-decoder-design-using-high-level-1abttlnjbm.pdf

Scalable and low power LDPC decoder design using high level algorithmic synthesis

This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput LDPC codes are widely adopted by the new emerging standards for wireless communication systems and storage applications due to their near-capacity error correcting performance To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding jobs among multi-processors in GPU In addition, we propose a scalable multi-codeword decoding scheme to fully utilize the computation resources of GPU Furthermore, we developed a novel adaptive performance-tuning method to make our decoder implementation more flexible and scalable The experimental results show that our LDPC decoder is scalable and flexible, and the adaptive performance-tuning method can deliver the peak performance based on the GPU architecture

/pdf/gpu-accelerated-scalable-parallel-decoding-of-ldpc-codes-4iew8c8m40.pdf

GPU accelerated scalable parallel decoding of LDPC codes

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 × 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps.

/pdf/high-throughput-soft-output-mimo-detector-based-on-path-5o0lpenn77.pdf

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures usually lead to different hardware implementations. In this paper, we propose a unified decoder architecture that is capable of decoding both LDPC and turbo codes with a limited hardware overhead. We employ maximum a posteriori (MAP) algorithm as a bridge between LDPC and turbo codes. We represent LDPC codes as parallel concatenated single parity check (PCSPC) codes and propose a group sub-trellis (GST) decoding algorithm for the efficient decoding of PCSPC codes. This algorithm achieves about 2X improvement in the convergence speed and is more numerically robust than the classical ldquotanhrdquo algorithm. What is more interesting is that we can generalize a unified trellis decoding algorithm for LDPC and turbo codes based on their trellis structures. We propose a reconfigurable computation kernel for log-MAP decoding of LDPC and turbo codes at a cost of ~15% hardware overhead. Small lookup tables (LUTs) with 9 entries of 2-bit data are designed to implement the log-MAP algorithm. Fixed point (6:2) simulation results show that there is negligible or nearly no performance loss by using this LUT approximation compared to the ideal case. The proposed architecture results in scalable and flexible datapath units enabling parallel decoding of LDPC/turbo codes.

/pdf/unified-decoder-architecture-for-ldpc-turbo-codes-10sl815fq5.pdf

Unified decoder architecture for LDPC/turbo codes

In a high performance multiple-input multiple-output (MIMO) system, a soft output MIMO detector combined with a channel decoder is often used at the receiver to maximize performance gain. Graphic processor unit (GPU) is a low-cost parallel programmable co-processor that can deliver extremely high computation throughput and is well suited for signal processing applications. We propose and implement a novel soft MIMO detection algorithm and show we meet real-time performance while maintaining flexibility using GPU.

/pdf/reconfigurable-real-time-mimo-detector-on-gpu-4ess9kogy3.pdf

Yang Sun

Papers

Scalable and low power LDPC decoder design using high level algorithmic synthesis

GPU accelerated scalable parallel decoding of LDPC codes

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

Unified decoder architecture for LDPC/turbo codes

Reconfigurable real-time MIMO detector on GPU