IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.

Progress and challenges in VLSI placement research

Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated in modern design flow; 2) a new problem formulation for post-placement optimization with multi-bit flip-flops; 3) flip-flop clustering and placement algorithms to simultaneously minimize flip-flop power consumption and interconnecting wirelength; and 4) a progressive window-based optimization technique to reduce placement deviation and improve runtime efficiency of our algorithms Experimental results show that our algorithms are very effective in reducing not only flip-flop power consumption but also clock tree and signal net wirelength Consequently, the power consumption of the clock network is minimized

Post-Placement Power Optimization With Multi-Bit Flip-Flops

Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Given a design, we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wirelength is also considered. The time complexity of our algorithm is Θ(n1.12) less than the empirical complexity of Θ(n2). According to the experimental results, our algorithm significantly reduces clock power by 20-30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.

/pdf/effective-and-efficient-approach-for-power-reduction-by-56dgqk5491.pdf

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Given the significance of placement in integrated circuit (IC) physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress leading up to the state of the art, and outstanding challenges.

Progress and Challenges in VLSI Placement Research

Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.

Post-placement power optimization with multi-bit flip-flops

In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption of the clock network usually dominates the dynamic power of the chip due to its highest switching rate. To effectively minimize the power consumption of the clock network, recent studies have been investigating the usage of multi-bit flip-flops (MBFFs). This paper presents the advantages of applying MBFFs, introduces various MBFF design flows, surveys key techniques for design optimization with MBFFs, and provides some future research directions in clock power saving with MBFFs.

Recent research in clock power saving with multi-bit flip-flops

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger bit numbers as possible to gain more clock power saving. However, an MBFF with a larger bit number may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. To address the problem, this paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different bit numbers. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization. To our best knowledge, this is also the first work in the literature that considers the crosstalk effect for the MBFF application.

https://www.researchgate.net/profile/Mark_Lin5/publication/241627004_Crosstalk-aware_power_optimization_with_multi-bit_flip-flops/links/559a929d08ae5d8f3937dd0c.pdf

Yao-Tsung Chang

Papers

Post-Placement Power Optimization With Multi-Bit Flip-Flops

Post-placement power optimization with multi-bit flip-flops

Recent research in clock power saving with multi-bit flip-flops

Crosstalk-aware power optimization with multi-bit flip-flops

Crosstalk-aware multi-bit flip-flop generation for power optimization