Showing papers by "Yasuhiro Sugimoto published in 2001"

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

Abstract: A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-/spl mu/m MOS devices with normal threshold voltages (V/sub th/) of +0.7 V (nMOS) and -0.7 V (pMOS).

Sample-and-hold circuit and A/D converter

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow. There is provided a common phase feedback circuit 2, common phase feedback hold capacitors CF1 and CF2 of which are connected to input terminals IN1 and IN2 of a completely differential type operational amplifier circuit 1, during a sample period, by way of reset switches RS1 and RS2 connecting the input terminals IN1 and IN2 and output terminals OUT1 and OUT2 of the completely differential type operational amplifier circuit 1, the common phase feedback hold capacitors CF1 and CF2 are charged to thereby determine a balance point of a middle value of differential output signals from the output terminals OUT1 and OUT2 and during a hold period, the balance point of the middle value of the differential output signals is maintained by electric charge charged to the common phase feedback hold capacitors CF1 and CF2 regardless of the differential output signals.

A 1 V operational, 20 MS/s and 57 dB of S/N, current-mode CMOS sample-and-hold IC

Abstract: A 1 V operational, 20 MS/s MOS sample-and-hold IC, which is applicable to video signal processing, has been developed. The signal-to-noise ratio (SNR) reached 57 dB under the application of +200 μA of differential input signal current at a 1 MHz frequency. The fabrication process was 0.35 μm CMOS with a threshold voltage of +0.35 V for an NMOS device and -0.35 V for a PMOS device.

Cascode amplifying circuit and folded cascode amplifying circuit

Abstract: To provide a cascode amplifying circuit having large amplifying gain without narrowing an output operational range or deteriorating response performance of the circuit even with a constitution by a small number of elements is achieved by applying negative feedback from the source to the gate of an MOS transistor M 2 provided with an output terminal at the drain via the source and the drain of an MOS transistor M 3 of N-channel type, the source and the drain of an MOS transistor M 4 of P-channel type and a current mirror constituted by MOS transistors M 5 and M 6 of N-channel type. By this constitution, operation of the MOS transistor M 3 is not effected with influence of lowering of voltage of the source of the MOS transistor M 2, a wide output operational range is provided and mirror effect with respect to gate/drain capacitance of the MOS transistor is restrained to thereby restrain a reduction in response speed.

Differential comparison circuit

Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit. Therefore, the differential comparison circuit can set the reference voltage to the differential signal and can easily obtain required accuracy.