Showing papers by "Yasuhiro Sugimoto published in 2002"

Differential comparator circuit

Abstract: PROBLEM TO BE SOLVED: To provide a differential comparator circuit, in which desired circuit precision, is easily obtained and which is capable of comparing difference signals with little influence of the fluctuation of a power supply voltage or the like. SOLUTION: Input and output terminals I/O1 and I/O2 of a latch circuit 1 are respectively connected to the respective drain terminals of MOS transistors M1 and M2 whose characteristics are the same, and input terminals IN1 and IN2 are respectively provided to the gate terminal and source terminal of the MOS transistor M2, and input terminals IN3 and IN4 are respectively provided to the gate terminal and source terminal of the MOS transistor M2, and the MOS transistors M1 and M2 are turned into the same bias state by a bias circuit 2. The difference between the input signals to be supplied to the input terminals IN1 and IN2 and the difference between the input signals to be supplied to the terminals IN3 and IN4 are compared, and the compared result is outputted from the first and second input and output terminals I/O1 and I/O2 so that it is possible to prevent the influence of any input offset voltage. Also, it is possible to obtain a reference voltage as a differential signal, and to easily obtain necessary precision.

Cascode amplifier circuit and folded cascode amplifier circuit

Abstract: PROBLEM TO BE SOLVED: To provide a cascode amplifier circuit having a large amplification gain without narrowing an output operation range nor damaging the responsiveness of the circuit although it is constituted of a small number of elements. SOLUTION: Negative feedback is performed from the source to gate of an MOS transistor M2 whose drain is provided with an output terminal, through the source and drain of an N channel type MOS transistor M3, the source and drain of a P channel type MOS transistor M4, and a current mirror constituted of N channel type MOS transistors M5 and M6. Thus, the operation of the MOS transistor M3 can be prevented from being affected by the decreases of the voltage of the source of the MOS transistor M2, and a wide output operation range can be obtained. Also, mirror effects on the gate and drain capacity of the MOS transistor can be reduced, and the deterioration of a responding speed can be reduced.