Showing papers by "Yasuhiro Sugimoto published in 2007"

A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme

Abstract: A CMOS Current-mode DC-DC converter using a quadratic slope compensation scheme is presented. The use of a quadratic slope instead of a conventional linear slope makes a damping factor and a frequency bandwidth of a current feedback loop independent of the converter's output voltage. Further designing the coefficient of the quadratic slope to be fully dependent of the input voltage, the damping factor and the frequency bandwidth become completely independent of both the input and output voltages. A test chip of a buck converter in a 5 MHz operation which uses a quadratic slope compensation scheme has been fabricated by using a 0.35 mum CMOS process. The evaluation results show that with a current capability of up to 500 mA the frequency characteristics of the total loop are constant when the input and output voltages change from 3.3 V to 2.5 V and from 2.5 V down to 0.5 V, respectively, and also that the recovery time is 50 mus with a peak voltage deviation of less than 50 mV for load current changes from 20 mA to 200 mA and vice versa.

A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain

Abstract: A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bit-block, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 mum CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional V BE Amplification Scheme

Abstract: This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional V BE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified V T (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25V is required, the voltage gain of the amplifier for V BE becomes less than one, and the voltage gain of the amplifier for V T becomes small. This enables the size of bipolar transistors for V T generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-pm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of46ppm/°C over 130°C change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 7μA of current consumption in the voltage reference part, and a 6% change over 130°C change for the 13μA current source.

A Study to Realize a 1-V Operational Passive Σ-Δ Modulator by Using a 90 nm CMOS Process

Abstract: Summary A 1-V operational sigma-delta modulator with a second-order passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.

LETTER Special Section on Analog Circuits and Related SoC Integration Technologies A Study to Realize a 1-V Operational Passive Σ-∆ Modulator by Using a 90nm CMOS Process

Abstract: SUMMARY A 1-V operational sigma-delta modulator with a secondorder passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture

Abstract: This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.