A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log b N indicates a ceiling function providing the smallest integer not less than log b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Reconfigurable, fault tolerant, multistage interconnect network and protocol

In fast packet-switching networks, packets of particular connections (CS1, CS2) (e.g., voice, moving-image) are to be treated with priority over packets of other connections (PS1, PS2, PS3) (e.g., data) (without delay jitter and loss of information). Prior art arrangements are divided into a circuit-switching portion (for CS1, CS2) and a packet-switching portion (for PS1, PS2, PS3). The circuit-switching portion operates on a time-division multiplex basis. On each incoming line, 70 packets each containing 40 octets, for example, are combined into a frame. If no special steps were taken, delays on the order of 40×70×8 bits=22,400 bits would result in each switching stage; for each input of a switching stage, 22,400 bits of storage would be necessary. According to the invention, all packets are divided within the exchange, into subpackets of equal length and distributed to subframes. Switching takes place on the basis of subframes. Delays and memory location requirements are reduced in the ratio of frames:subframes. Preferably, the connections (CS1, CS2) to be treated with priority are assigned fixed positions in each frame and each subframe throughout the call. Subpackets of the other packets are preferably inserted in sequence into free positions, and are recombined into complete packets within each switching stage.

Method and facilities for hybrid packet switching

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 logb N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and logb N indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Multiprocessor computer system

Communication system uses diagnostic processors and master processor module to identify faults and generate mapping tables to reconfigure communication paths in a multistage interconnect network

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Computer system using a master processor to automatically reconfigure faulty switch node that is detected and reported by diagnostic processor without causing communications interruption

This invention relates to a method of switching voice and data over a multistage interconnection network (MIN). More specifically, a plurality of bits are stored in respective storage locations of the switching elements of the MIN. Storage location of a switching element represents a particular time slot in a frame or a sequence of frames. Bits stored in each location represent specific conditions of the inputs and outputs of the switching elements and also indicate which inputs of the switching elements will be connected to which outputs of the switching elements. This storage of control information in the switching elements allows the switching network to rapidly and simultaneously change connections through the switching elements of the network.

Distributed bit switching of a multistage interconnection network

In a method for switching voice and data over a multistage interconnection network (MIN) (10), a plurality of bits are stored in respective storage locations (2-1, 2-2, ... 2-512) of the switching elements (5) of the MIN. Each storage location of a switching element represents a particular time slot in a frame or a sequence of frames. Bits (27, 26) stored in each location represent specific conditions of the inputs and outputs of the switching elements and also indicate which inputs of the switching elements will be connected to which outputs of the switching elements. This storage of control information in the switching elements allows the switching network to rapidly and simultaneously change connections through the switching elements of the network.

Yeong-Chang Lien

Papers

Distributed bit switching of a multistage interconnection network

A method of controlling a multi-stage interconnection network

Steuerverfahren für ein mehrstufiges Vermittlungsnetz