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Patent

Distributed bit switching of a multistage interconnection network

TLDR
In this paper, a plurality of bits are stored in respective storage locations of the switching elements of a multistage interconnection network (MIN), where each storage location represents a particular time slot in a frame or a sequence of frames.
Abstract
This invention relates to a method of switching voice and data over a multistage interconnection network (MIN). More specifically, a plurality of bits are stored in respective storage locations of the switching elements of the MIN. Storage location of a switching element represents a particular time slot in a frame or a sequence of frames. Bits stored in each location represent specific conditions of the inputs and outputs of the switching elements and also indicate which inputs of the switching elements will be connected to which outputs of the switching elements. This storage of control information in the switching elements allows the switching network to rapidly and simultaneously change connections through the switching elements of the network.

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Citations
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Patent

Reconfigurable, fault tolerant, multistage interconnect network and protocol

TL;DR: In this paper, a multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network is proposed.
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Method and facilities for hybrid packet switching

TL;DR: In this article, all packets are divided within the exchange, into subpackets of equal length and distributed to subframes, and switching takes place on the basis of subframes.
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Multiprocessor computer system

TL;DR: In this article, a multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network is proposed.
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Communication system uses diagnostic processors and master processor module to identify faults and generate mapping tables to reconfigure communication paths in a multistage interconnect network

TL;DR: In this paper, a multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network is proposed.
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Computer system using a master processor to automatically reconfigure faulty switch node that is detected and reported by diagnostic processor without causing communications interruption

TL;DR: In this article, a multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network is built using interconnected switch nodes arranged in 2.
References
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Journal ArticleDOI

Virtual cut-through: A new computer communication switching technique

TL;DR: The analysis shows that cut-through switching is superior (and at worst identical) to message switching with respect to the above three performance measures.
Patent

Distributed voice-data switching on multi-stage interconnection networks

TL;DR: In this article, the authors proposed a method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network.
Patent

Method of transmitting information and multiplexing device for executing the method

TL;DR: In this paper, a TDM multiplexer is used to combine circuit-switched synchronous data and packetswitched asynchronous data for transmission over a common channel, where the remaining capacity of the TDM frame is used for transmission of store-and-forward traffic which is inserted in the gaps between assigned time slots in the form of an intermittent bit stream.
Patent

Nonblocking self-routing packet and circuit switching network

TL;DR: In this article, the authors propose a packet switching architecture in which switching network nodes automatically determine nonblocking paths through a switching network in response to address information, and each node upon receipt of the acknowledge signal establishes the path through the itself.
Patent

Distributed packet switching arrangement

TL;DR: An integrated packet switching and circuit switching comprising a number of switching modules (1000) each connected to a corresponding plurality of user terminals (1002) is described in this paper, where each switching module includes a time slot interchange unit (1011) for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit.