IEEE International Solid-State Circuits Conference

An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

Method and apparatus for interrogating electronic equipment components

Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-/spl mu/m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm/sup 2/ of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW.

/pdf/a-1-5-v-14-bit-100-ms-s-self-calibrated-dac-3skfsu7w79.pdf

A 1.5-V 14-bit 100-MS/s self-calibrated DAC

For a current-steering digital-to-analog converter (DAC) without an extra output stage, the variation of the output voltage will result in the variation of the output delay. These output-dependent delay differences will deteriorate the spurious-free dynamic range (SFDR) of a high-speed high-accuracy DAC, especially when glitches exist. In this paper, a convenient mathematical model is presented to analyze during design the impact of this kind of delay differences on the SFDR. The results are verified by comparison to the results of more detailed simulations. Also the impact of glitches on this effect is demonstrated. Possible solutions to reduce this impact are discussed and summarized

/pdf/the-analysis-and-improvement-of-a-current-steering-dac-s-2j4y8vrup7.pdf

The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR—II: The Output-Dependent Delay Differences

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm2, among which the area of the current-source block is only 0.28 mm2. The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.

A 14-bit 200-MHz Current-Steering DAC with Switching Sequence Post-Adjustment Calibration

This paper discusses switching schemes for gradient error compensation in unary (thermometer-decoded) arrays of digital-to-analog converters (DACs). The absolute lower bound of integral nonlinearity (INL) by optimizing switching sequences is established and optimal switching sequences that meet the lower bound of INL are presented for linear error compensation in one-dimensional arrays. A rapidly converging algorithm is developed to obtain INL bounded switching sequences for any given type of gradient error compensation. Simulation results show that the new switching sequences substantially reduce the nonlinearity of DACs due to gradient errors.

http://class.ece.iastate.edu/vlsi2/docs/Papers%20Done/2000-06-TCAS2-YC.pdf

Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays

Current source mismatch is a major source of nonlinearity in current-steering digital-to-analog converters (DAC). In order to achieve a given linearity specification at a given yield level, it is essential that the designer determine the:: minimum required matching accuracy of the unit current sources. Monte-Carlo simulations are very time-consuming and provide the designer with little insight to choose proper DAC architectures and make tradeoff between design specifications. The limited mathematical formulations that have appeared in the literature are based on nonstandard linearity definitions or oversimplifying statistical assumptions. In this paper, simple formulas are obtained that accurately describe the relationship between nonlinearity, bits of resolution, minimum required matching accuracy, and yield, which make it possible to optimize the DAC structure and achieve high performance with less cost and power consumption.

Formulation of INL and DNL yield estimation in current-steering D/A converters

Modified wide-swing cascode current mirrors are introduced that achieve low input and output voltage drops. The new structures can be used in low-voltage environments and provide even higher output impedance than regular cascoded current mirrors. With dynamic biasing, high current accuracy and high output impedance can be maintained over a large operating current range.

Cascode current mirrors with low input, output and supply voltage requirements

Gradient error can be compensated by optimizing switching sequences of DAC arrays. This paper establishes an absolute lower bound of integral nonlinearity (INL) which may be achieved by optimizing switching sequences. Optimal switching sequences that meet this lower bound are presented for one-dimensional linear gradient error compensation in unary (thermometer decoded) DAC arrays. The sequences can be used in row-column decoded current or capacitor unary arrays as well as R-string DACs, where the switching sequence is optimized in one dimension.

/pdf/optimal-switching-sequences-for-one-dimensional-linear-19pz8430bg.pdf

Yonghua Cong

Papers

A 1.5-V 14-bit 100-MS/s self-calibrated DAC

Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays

Formulation of INL and DNL yield estimation in current-steering D/A converters

Cascode current mirrors with low input, output and supply voltage requirements

Optimal switching sequences for one-dimensional linear gradient error compensation in unary DAC arrays