For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.

CMOS VLSI Design : A Circuits and Systems Perspective

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3- mu m CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described. >

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A CMOS transconductance-C filter technique for very high frequencies

A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3- mu m p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD >

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

Basic properties of the operational transconductance amplifier (OTA) are discussed. Applications of the OTA in voltage-controlled amplifiers, filters, and impedances are presented. A versatile family of voltage-controlled filter sections suitable for systematic design requirements is described. The total number of components used in these circuits is small, and the design equations and voltage-control characteristics are attractive. Limitations as well as practical considerations of OTA-based filters using commercially available bipolar OTAs are discussed. Applications of OTAs in continuous-time monolithic filters are considered.

/pdf/active-filter-design-using-operational-transconductance-2mzdfyvyv6.pdf

Active filter design using operational transconductance amplifiers: A tutorial

VLSI Design Techniques for Analog and Digital Circuits

Generation of two integrator loop filter structures using operational transconductance amplifiers (OTAs) and capacitors (TAC) is presented. A direct block diagram approach is used to generate the TAC filter structures. The basic filter building blocks consist of a lossless integrator, lossy integrators and the three types of summers. They are implemented using OTAs as the active components. The resulting TAC second-order filter structures, some previously reported and others new structures, are generated in an orderly way. It is shown that the selection of the best structure depends on the particular application or design specifications. The generated TAC biquadratic structures are only very suitable for monolithic filters since typically only OTAs and two capacitors are needed. A TAC filter structure homologous to the conventional KHN op amp filter structure is presented. Programmability of omega /sub p/, Q/sub p/ and voltage gain is considered. >

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Generation of continuous-time two integrator loop OTA filter structures

When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-/spl mu/m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm/sup 2/ of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW.

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Randall L. Geiger

Papers

Active filter design using operational transconductance amplifiers: A tutorial

VLSI Design Techniques for Analog and Digital Circuits

Generation of continuous-time two integrator loop OTA filter structures

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

A 1.5-V 14-bit 100-MS/s self-calibrated DAC