Disclosed are a liquid crystal display device which reduces the number of masks and improves an aperture ratio, and a method for fabricating the same. The liquid crystal display device includes gate and data lines perpendicularly intersecting on a substrate having pixel and pad parts; a thin film transistor on the substrate at the intersection of the gate and data lines; a pixel electrode on the substrate at the pixel part and connected directly to a drain electrode of the thin film transistor; an insulating film on the overall surface of the substrate including the pixel electrode and the thin film transistor; an organic film on the insulating film over the thin film transistor and the data line; and a common electrode of slit shapes overlapping the pixel electrode such that the insulating film is interposed between the common electrode and the pixel electrode.

Liquid crystal display device and method for fabricating the same

A high performance interconnection network on a chip is essential to match the ever improving performance of the semiconductor devices they interconnect. This issue reviews the need, some fundamental background justifying the need, approaches one can take in trying to satisfy the need, and associated issues related to the concept of multilevel interconnection (MLI) technology for the ULSI/GSI era of the silicon integrated circuits, with emphasis on materials and the processes that will lead to an acceptable MLI scheme. Thus besides discussing the MLI concepts and implementation issues, properties of metals and their alloys (especially those of Cu and Al), diffusion barrier/adhesion promoter, interlayer dielectrics, deposition and etching of mateials, planarization issues, reliability issues, and new materials concepts are presented. Emphasis is obviously placed on the presently focused research on replacing aluminum with copper based interconnections. The author's viewpoint on gradual changes in replacing current materials with newer mateials as they become available is also presented. A synergism between the materials sets for on-chip and off-chip interconnections has been pointed out.

Multilevel interconnections for ULSI and GSI era

An intensive study has been performed to understand and tune deep reactive ion etch (DRIE) processes for optimum results with respect to the silicon etch rate, etch profile and mask etch selectivity (in order of priority) using state-of-the-art dual power source DRIE equipment. The
research compares pulsed-mode DRIE processes (e.g. Bosch technique) and mixed-mode DRIE processes (e.g. cryostat technique). In both techniques, an inhibitor is added to
fluorine-based plasma to achieve directional etching, which is formed out of an oxide-forming (O2) or a fluorocarbon (FC) gas (C4F8 or CHF3). The inhibitor can be introduced together with the etch gas, which is named a mixed-mode DRIE process, or the inhibitor can be added in a
time-multiplexed manner, which will be termed a pulsed-mode DRIE process. Next, the most convenient mode of operation found in this study is highlighted including some remarks to
ensure proper etching (i.e. step synchronization in pulsed-mode operation and heat control of the wafer). First of all, for the fabrication ......
 Enjoy reading . Henri Jansen 18 June 2008

https://iopscience.iop.org/article/10.1088/0960-1317/19/3/033001/pdf

Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment

A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

Methods of forming an interconnect on a semiconductor substrate

The investigation of copper for use as an interconnection metal in the ultra large-scale integration (ULSI) era of silicon integrated circuits has accelerated in the past several years. The obvious advantages for using copper to replace currently used Al are related to its lower resistivity (1.7 μΩ-cm vs. 2.7 μω-cm for Al) and its higher electromigration resistance (several orders of magnitude higher compared with Al). The goal of this review is to examine the properties of copper and its applicability as the interconnection metal. A comparison of electromigration behavior of various possible interconnection metal in standard “bulk” state is made. This is followed by a review of the calculations made comparing (a) the RC (resistance × capacitance) time constants of various material systems and (b) the joule heating of the interconnection materials. A comparative study of various metal systems for the application as the interconnect metal is then made. These discussions will clearly establish the ...

Copper metallization for ULSL and beyond

A process for growing a thin metallic film of gold or copper selectively on a predetermined area of a substrate. An organic complex or organometallic compound of gold or copper as a starting material is heated to evaporate the same, while a substrate having on the surface thereof a metal or a metallic silicide as a first material and an oxide or a nitride as a second material is heated at a temperature equal to or higher than the decomposition temperature, on the first material, of a vapor of the starting material. The vapor of the evaporated starting material is fed together with a reducing gas onto the heated substrate to selectively grow a thin metallic film of gold or copper only on the surface of the first material.

Process for selectively growing thin metallic film of copper or gold

The trench shape formation mechanism is examined during reactive ion etching (RIE) of single‐crystal silicon using chlorine for the etching gas, and shape control is achieved through the mixing of the depositing gas. One problem with RIE is undercutting of the sidewall due to divergent ions from ion‐molecule collisions. Furthermore, sharp crevices are formed at the trench bottom edges because of the increase in radical concentration at these edges. From the experiment using chlorine, it is found that these problems are suppressed by a simultaneous deposition. Next, this deposition is shown to be enhanced by mixing hydrogen with the chlorine. However, for complete suppression of the crevice growth, silicon tetrachloride must be added to the mixture. Using this procedure, the desired tapering sidewall slope was obtained by controlling both the deposition rate and RF power density. Experimentation showed that the etched depth is independent of the trench width for trenches wider than 0.7 μm, although the sidewall slope only slightly decreased with increasing trench width. Consequently, silicon trench etching in a chlorine, hydrogen, and silicon tetrachloride mixture is a promising method for many silicon trench applications, because of its high shape controllability and less chance of contamination.

Etched Shape Control of Single‐Crystal Silicon in Reactive Ion Etching Using Chlorine

Reactive ion etching of Cu films in SiCl4 and N2 is proposed for the fabrication of copper interconnection lines in LSIs. Cu films can be etched using a wafer heated to at least 250°C. Adding N2 to SiCl4 has two advantages. One is that it prevents the etching rate of Cu between narrow pattern spaces from decreasing because it removes organic material on Cu films near resist patterns. The other is that it forms protective films such as SiN on the side walls of Cu patterns and prevents side etching. The side wall taper is controlled by changing the N2 flow percentage.

https://iopscience.iop.org/article/10.1143/JJAP.28.L1070/pdf

Reactive Ion Etching of Copper Films in SiCl4 and N2 Mixture

Selective copper CVD technique involving hydrogen reduction of hexafluoro acetylacetonate copper has been used to fill vias for fabricating double-level copper interconnect structure. The surface morphology of selectively deposited copper on copper substrate of the via bottom depends strongly on via opening process. A two-step via opening process consisting of an reactive ion etching of the insulating interlayer and a wet removal of the interlayer metal results in smooth copper plug formation by CVD. Double-level copper interconnect structures have been fabricated using this technique and a via resistance as low as 100 mΩ has been obtained for a 1 μ diameter via.

Double-level copper interconnections using selective copper CVD

Plasma enhanced copper chemical vapor deposition (CVD) using acetyl-acetonato copper as a source compound is investigated for VLSI metallization. Results show that electrical resistivity and film morphology are greatly dependent on substrate temperature, and that plasma enhancement results in smooth copper film formation. Hydrogen is essential for reducing oxygen and carbon incorporation of copper film. A smooth surface film of low electrical resistivity (1.8 µΩcm) is obtained by plasma-enhanced CVD with hydrogen carrier gas at the substrate temperatures between 200°C and 280°C. Investigation of the step coverage of the film results in the coverage of the trench being superior to that of the sputtering method.

Yoshinobu Arita

Papers

Process for selectively growing thin metallic film of copper or gold

Etched Shape Control of Single‐Crystal Silicon in Reactive Ion Etching Using Chlorine

Reactive Ion Etching of Copper Films in SiCl4 and N2 Mixture

Double-level copper interconnections using selective copper CVD

Plasma-Enhanced Chemical Vapor Deposition of Copper