Promising for digital signal processing applications, approximate computing has been extensively considered to tradeoff limited accuracy for improvements in other circuit metrics such as area, power, and performance. In this paper, approximate arithmetic circuits are proposed by using emerging nanoscale spintronic devices. Leveraging the intrinsic current-mode thresholding operation of spintronic devices, we initially present a hybrid spin-CMOS majority gate design based on a composite spintronic device structure consisting of a magnetic domain wall motion stripe and a magnetic tunnel junction. We further propose a compact and energy-efficient accuracy-configurable adder design based on the majority gate. Unlike most previous approximate circuit designs that hardwire a constant degree of approximation, this design is adaptive to the inherent resilience in various applications to different degrees of accuracy. Subsequently, we propose two new approximate compressors for utilization in fast multiplier designs. The device-circuit SPICE simulation shows 34.58% and 66% improvement in power consumption, respectively, for the accurate and approximate modes of the accuracy-configurable adder, compared to the recently reported domain wall motion-based full adder design. In addition, the proposed accuracy-configurable adder and approximate compressors can be efficiently utilized in the discrete cosine transform (DCT) as a widely-used digital image processing algorithm. The results indicate that the DCT and inverse DCT (IDCT) using the approximate multiplier achieve $\sim$ 2x energy saving and 3x speed-up compared to an exactly-designed circuit, while achieving comparable quality in its output result.

https://par.nsf.gov/servlets/purl/10094214

Majority-Based Spin-CMOS Primitives for Approximate Computing

Approximate computing is the idea that systems can gain performance and energy efficiency if they expend less effort on producing a “perfect” answer. Approximate computing techniques propose various ways of exposing and exploiting accuracy–efficiency tradeoffs. We present a taxonomy that classifies approximate computing techniques according to salient features: visibility, determinism, and coarseness. These axes allow us to address questions about the correctability, reproducibility, and control over accuracy–efficiency tradeoffs of different techniques. We use this taxonomy to inform research challenges in approximate architectures, compilers, and applications.

A Taxonomy of General Purpose Approximate Computing Techniques

Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered the explosive growth of AI workloads across the spectrum of computing devices. However, their superior accuracy comes at a high computational cost, which necessitates approaches beyond traditional computing paradigms to improve their operational efficiency. Leveraging the application-level insight of error resilience, we demonstrate how approximate computing (AxC) can significantly boost the efficiency of AI platforms and play a pivotal role in the broader adoption of AI-based applications and services. To this end, we present RaPiD, a multi-tera operations per second (TOPS) AI hardware accelerator core (fabricated at 14-nm technology) that we built from the ground-up using AxC techniques across the stack including algorithms, architecture, programmability, and hardware. We highlight the workload-guided systematic explorations of AxC techniques for AI, including custom number representations, quantization/pruning methodologies, mixed-precision architecture design, instruction sets, and compiler technologies with quality programmability, employed in the RaPiD accelerator.

Efficient AI System Design With Cross-Layer Approximate Computing

Energy efficiency is one of the most crucial constraints that dictate performance, lifetime, form factor, and cost in modern computing system design. However, the energy efficiency improvement driven by semiconductor technology scaling is coming to an end with the prediction of the end of Moore’s law in the near future. Approximate computing is a new paradigm to accomplish energy-efficient computing in this twilight of Moore’s law by relaxing exactness requirement of computation results for intrinsically error-resilient applications, such as some machine learning and signal processing. In this paper, we propose an approximate binary divider design that features dynamic configurability of accuracy and energy consumption. Conventional approximate binary dividers lack runtime energy-quality scalability, which is the key to maximizing energy efficiency while meeting the dynamically varying accuracy requirements of the application. Our divider, named Scalable Accuracy Approximate Divider with Error Compensation (SAADI-EC), supports dynamic energy-quality scalability by the incremental approximation of the reciprocal of the divisor using Taylor series expansion. As a result, the speed and energy efficiency of division can be dynamically traded for accuracy by controlling the number of iterations for the approximation. In addition, SAADI-EC corrects the approximation error using simple, yet effective error compensation hardware to greatly improve the accuracy compared to the base implementation, SAADI. For the 8-bit approximation of 32-bit/16-bit division, the average accuracy of SAADI-EC can be adjusted from 94.2% to 99.6% by varying latency and energy $7\times $ . In terms of $\text {energy}\times \text {delay}$ cost, our design costs up to 87% less than other approximate binary dividers for the same accuracy level. We evaluate the accuracy and energy consumption of SAADI-EC for various design parameters and demonstrate its efficacy for low-power signal processing applications including ${k}$ -means color quantization, JPEG image compression, and image division for video sequences.

SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency

Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are proposing voltage over-scaling based approximate operators for applications that can tolerate errors. We characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing scheme and clock frequency) to generate models for approximate operators. Error-resilient applications can be mapped with the generated approximate operator models to achieve optimum trade-off between energy efficiency and error margin. Based on the dynamic speculation technique, best possible operating triad is chosen at runtime based on the user definable error tolerance margin of the application. In our experiments in 28nm FDSOI, we achieve maximum energy efficiency of 89% for basic operators like 8-bit and 16-bit adders at the cost of 20% Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime.

/pdf/pushing-the-limits-of-voltage-over-scaling-for-error-ykb47jw4xa.pdf

Pushing the limits of voltage over-scaling for error-resilient applications

Approximate computing is an emerging paradigm to improve the efficiency of computing systems by leveraging the intrinsic resilience of applications to their computations being executed in an approximate manner. Prior efforts on approximate hardware design have largely focused on circuit-level techniques. We propose a new approach, clock overgating, for the design of approximate circuits at the Register Transfer Level (RTL). The key idea is to gate the clock signal to selected Flip-Flops (FFs) in the circuit, even during execution cycles in which the circuit functionality is sensitive to their state. This saves power in the clock tree, the FF itself and in its downstream logic, while a quality loss ensues if the erroneous FF state propagates to the circuit output. We develop a systematic methodology to identify an energy-efficient overgating configuration for any given circuit and quality constraint. Towards this end, we develop 3 key strategies — significance-based overgating, grouping FFs into overgating islands, and utilizing internal signals of the circuit as triggers for overgating — that efficiently prune the large space of possible overgating configurations. We evaluate clock overgating by designing approximate versions of 6 machine learning accelerators, and demonstrate energy benefits of 1.36x on average (and upto 1.80x) for negligible (<0.5%) loss in application quality (classification accuracy).

https://dl.acm.org/doi/pdf/10.1145/2897937.2898005

Designing approximate circuits using clock overgating

Approximate Computing (AxC), which leverages the intrinsic resilience of applications to approximations in their underlying computations, has emerged as a promising approach to improving computing system efficiency. Most prior efforts in AxC take a compute-centric approach and approximate arithmetic or other compute operations through design techniques at different levels of abstraction. However, emerging workloads such as machine learning, search and data analytics process large amounts of data and are significantly limited by the memory sub-systems of modern computing platforms.In this work, we shift the focus of approximations from computations to data, and propose a data-centric approach to AxC, which can boost the performance of memory-subsystem-limited applications. The key idea is to modulate the application’s data-accesses in a manner that reduces off-chip memory traffic. Specifically, we propose a data-access approximation technique called data subsetting, in which all accesses to a data structure are redirected to a subset of its elements so that the overall footprint of memory accesses is decreased. We realize data subsetting in a manner that is transparent to hardware and requires only minimal changes to application software. Recognizing that most applications of interest represent and process data as multi-dimensional arrays or tensors, we develop a templated data structure called SubsettableTensor that embodies mechanisms to define the accessible subset and to suitably redirect accesses to elements outside the subset. As a further optimization, we observe that data subsetting may cause some computations to become redundant and propose a mechanism for application software to identify and eliminate such computations. We implement SubsettableTensor as a C++ class and evaluate it using parallel software implementations of 7 machine learning applications on a 48-core AMD Opteron server. Our experiments indicate that data subsetting enables 1.33×–4.44× performance improvement with <0.5% loss in application-level quality, underscoring its promise as a new approach to approximate computing.

Data Subsetting: A Data-Centric Approach to Approximate Computing

Approximate Computing (AxC) is a popular design paradigm wherein selected computations are executed approximately to gain efficiency with minimal impact on application-level quality. Most efforts in AxC target specialized accelerators and domain-specific processors, with relatively limited focus on General-Purpose Processors (GPPs). However, GPPs are still broadly used to execute applications that are amenable to AxC, making AxC for GPPs a critical challenge. A key bottleneck in applying AxC to GPPs is that their execution units account for only a small fraction of total energy, requiring a holistic approach targeting compute, memory and control front-ends. This paper proposes such an approach that leverages the application property of value similarity, i.e., input operands to computations that occur close-in-time take similar values. Such similar computations are dynamically pre-detected and the fetch-decode-execute of entire instruction sequences are skipped to benefit performance. To this end, we propose a set of lightweight micro-architectural and ISA extensions called VSX that enable: (i) similarity detection amongst values in a cache-line, (ii) skipping of pre-defined instructions and/or loop iterations when similarity is detected, and (iii) substituting outputs of skipped instructions with saved results from previously executed computations. We also develop compiler techniques, guided by user annotations, to benefit from VSX in the context of common Machine Learning (ML) kernels. Our RTL implementation of VSX for a low-power RISC-V processor incurred 2.13% area overhead and yielded 1.19×-3.84× speedup with <0.5 % accuracy loss on 6 ML benchmarks.

Value Similarity Extensions for Approximate Computing in General-Purpose Processors

Approximate circuits are the basic hardware building blocks of approximate computing platforms. Manual approximate designs of simple arithmetic circuits (adders and multipliers) have demonstrated the potential for efficiency improvements using approximate circuits. However, their broader adoption requires systematic methodologies that can create approximate implementations for any arbitrary circuit. An approximate circuit can be viewed as realizing a logic function that slightly deviates from the original specification, while falling within a specified quality constraint. A design automation methodology should therefore enable the generation of “correct-by-construction” approximate circuits that are guaranteed to satisfy designer-specified quality constraints.

Automatic Synthesis Techniques for Approximate Circuits

Employing GPU to accelerate stream data processing has shown to be a considerable success in recent research. The stream processing engines need to process continuous data. Persistent Thread (PT), where GPU threads remain in a loop throughout executions, rather than non-Persistent Thread (nonPT) kernels can give several advantages. PT provides high-performance low-latency data processing by reducing kernel launch overhead and hiding memory copy overhead to the GPU. In this paper, we comparatively analyze the performances of PT and nonPT in various aspects. We also figure out the cause of advantages and what needs to be considered in order to obtain actual performance gain. The evaluation was done with four distinct application scenarios and the result shows that PT yields at most x4.4 higher performance over nonPT under desirable conditions.

Younghoon Kim

Papers

Designing approximate circuits using clock overgating

Data Subsetting: A Data-Centric Approach to Approximate Computing

Value Similarity Extensions for Approximate Computing in General-Purpose Processors

Automatic Synthesis Techniques for Approximate Circuits

Comparative Analysis of GPU Stream Processing between Persistent and Non-persistent Kernels