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Yu-Ting Chen
Researcher at University of California, Los Angeles
Publications - 16
Citations - 586
Yu-Ting Chen is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: Cache & Throughput (business). The author has an hindex of 11, co-authored 16 publications receiving 450 citations.
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Journal ArticleDOI
Hydro-Seq enables contamination-free high-throughput single-cell RNA-sequencing for circulating tumor cells
Yu Heng Cheng,Yu Chih Chen,Eric Lin,Riley Brien,Seungwon Jung,Yu-Ting Chen,Woncheol Lee,Zhijian Hao,Saswat Sahoo,Hyun Min Kang,Jason Cong,Monika L. Burness,Sunitha Nagrath,Max S. Wicha,Euisik Yoon +14 more
TL;DR: Hydro-Seq is presented, a contamination-free high-throughput hydrodynamic scRNA-seq barcoding technique for rare CTCs and Transcriptome analysis of these cells provides insights into monitoring target therapeutics and processes underlying tumor metastasis.
Proceedings ArticleDOI
A Novel High-Throughput Acceleration Engine for Read Alignment
TL;DR: This paper proposes an architecture, tailored for varied input sizes as well as harnessing software pruning strategies, to accelerate S-W, and demonstrates a 26.4x speedup over a 24-thread Intel Has well Xeon server, and outperforms wave front-based implementations by up to 6x with the same FPGA resource.
Proceedings ArticleDOI
Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design
TL;DR: This work proposes a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM, and provides hardware-based mechanisms to dynamically reconfigure RHC on-the-fly based on the cache demand.
Proceedings ArticleDOI
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration
TL;DR: It is demonstrated how a straightforward integration with 1000x slowdown can be tuned into an efficient integration with 2.6x overall system speedup and 2.4x energy efficiency improvement.
Proceedings Article
When apache spark meets FPGAs: a case study for next-generation DNA sequencing acceleration
TL;DR: This paper conducts an in-depth analysis of challenges at single-thread, single-node multi- thread, and multi-node levels, and proposes solutions including batch processing and the FPGA-as-a-Service framework to address them.