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Design Of Analog Cmos Integrated Circuits

A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

System, method, and computer program product for improving memory systems

Pattern Recognition by Self-Organizing Neural Networks edited by Gail A. Carpenter and Stephan Grossberg, MIT Press, 1991, ISBN 0-262-03176-0.

Pattern Recognition by Self-Organizing Neural Networks

A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Three phase and polarity encoded serial interface

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

Orthogonal differential vector signaling

The present invention relates to technologies for integrated circuits and Large Area Integrated Circuits (LAICs), which are integrated circuits made from photo-repetition of one or several reticle image fields, stitched together on at least one lithographic process layer. It also relates to a specific class of LAIC that can connect to the contacts of other ICs placed on its surface, where specific contact detection algorithms means are disclosed. The innovations include means for defect tolerance of serial communication links, means for efficient diagnosis of short and stuck-at faults in regular reconfigurable network, means for a programmable interposer for rapid prototyping of 3D stacked chips, means to build efficient large area micro-system devices (LAMS), with distributed and configurable hierarchical structures for power supply, thermal regulation and signal propagation, means to reduce mechanical/thermal/thermo-mechanical issues in LAMS devices, means to propagate analog signal on a configurable digital network, means to predict thermo-mechanical stress peaks.

Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributed-sensors and electrical signal propagation

This paper introduces an innovative reconfigurable circuit board for rapid system prototyping. This system supports high pin-count packages and high density system integration requirements, and can be programmed to interconnect integrated circuits and other components at near-intra-chip density. This paper presents the concept and investigates several aspects related to its feasibility. Considered factors include technological and physical constraints; architectural and system aspects; design and technology considerations. Preliminary results are promising, confirming that this smart reconfigurable circuit board can be implemented using a wafer-scale approach in a mature and low-cost 6-metal layer CMOS 0.18 mum technology, with the associated classical design CAD tools and flow. The achieved contact density is sufficient to interconnect components packaged with todaypsilas peripheral I/O and fine-pitched BGA packages.

An active reconfigurable circuit board

In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Methods, apparatus, and systems for reducing interference on nearby conductors

This paper presents a programmable interconnection network for a novel multi-reticle integrated circuit providing a reconfigurable circuit board for rapid system prototyping. This multi-dimensional mesh grid network, called WaferNettrade, can actively interconnect any pair of pins of integrated circuits deposited on the configurable system board. Two crossbar architectures are implemented and compared, one based on crosspoints and one based on standard cell multiplexers. Implementation results show the feasibility of this proposed cell-based array network that could interconnect a very large number of nodes, spread over an area that could fill a whole wafer, using a typical 6-metal 0.18 mum CMOS technology.

An interconnection network for a novel reconfigurable circuit board

The hardware implementation of the fuzzy ART neural network applied to a demanding real time radar signal clustering problem is investigated. To obtain efficient solutions for implementing this neural network with dedicated hardware, the network's algorithm is reformulated, and then a novel fuzzy ART system architecture is proposed. This system architecture is composed of a global comparator and several identical elementary modules (EMs), each one emulating a number of neurons. The general architecture of each EM consists of a local comparator, dividers, neural processors, and a block of memory.

Yves Blaquiere

Papers

Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributed-sensors and electrical signal propagation

An active reconfigurable circuit board

Methods, apparatus, and systems for reducing interference on nearby conductors

An interconnection network for a novel reconfigurable circuit board

A VLSI architecture for fast clustering with fuzzy ART neural networks