In this paper, a model is proposed which can predict accurately both ac and noise performance (all four noise parameters: minimum noise figure NF min , equivalent noise resistance R n , optimized source resistance R opt and reactance X opt ) of MOSFETs based on s -parameter and noise measurements at microwave frequencies. This model includes the relevant high frequency noise sources (i.e. the channel thermal noise, the induced gate noise and its correlation with the channel thermal noise and the thermal noise from the gate and parasitic resistances). In order to confirm the accuracy of the model and obtain the intrinsic scattering and noise parameters of devices, two de-embedding techniques (probe pad equivalent circuit modeling and direct parasitic noise de-embedding) have been used to de-embed the probe pad parasitics from the measured noise and s -parameters of the device-under-test (DUT). In addition, because of the complexity of this noise model, a direct calculation technique for calculating the four noise parameters was developed based on the small-signal transistor's model. Finally, the impact of gate resistance, and the noise improvement using multi-finger gate design are investigated.

High frequency noise of MOSFETs I Modeling

1 f noise of the drain current SI vs drain-source voltage was studied in an LDD MOSFET. Analysis of the d.c. characteristics shows that the series resistance RDd, introduced by the LDD structure on the drain side, increases greatly with the external drain-source voltage VDS increasing towards the value of the effective gate voltage V G ∗ . Consequently, the internal drain-source voltage Vds and the channel current IDS are reduced. This is used successfully to explain why the experimental results of SI as a function of V DS /V G ∗ in an LDD MOSFET are at variance with those in a conventional MOSFET. Here a model and a procedure are proposed from which the internal drain-source voltage Vds and series resistance are obtained from measuring results. After recalculation of the experimentally observed SI in terms of channel current fluctuations, we find that SIch vs normalized internal drain-source voltage V ds /V G ∗ shows the same trend as in a conventional MOSFET. The role of RDd becomes more important as the value of V DS /V G ∗ increases. Owing to the fact that the influence of RDd becomes small in relation to the channel resistance itself, a long-channel device is affected less than one with a short channel.

An explanation of 1/f noise in LDD MOSFETs from the ohmic region to saturation

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

P-channel LDD MOSFETs with a p+-poly gate and an n+-poly gate are investigated. The p+-poly gate forms a surface channel and the n+-pol gate a bulk channel. A new method is proposed to use an L-array for extracting the low field mobility μ00, the mobility degradation coefficient θ, the channel length correction l′, and the parameters Rs0 and Rsv for the gate-voltage-dependent series resistance on the source side RsS = Rs0 + Rsv/VG∗. A bulk channel device has a higher μ00 value, a Rsv and a smaller series resistance RDd on the drain side than a surface channel device. The θ value and the gate-voltage-independent part of the series resistance Rs0 are about the same in both devices. Under the same external bias conditions, a surface channel MOSFET has a smaller current and a higher 1/f current noise than a bulk channel device. The 1/f noise parameter α is found to be independent of the effective gate voltage and of the channel length for both defices. The bulk channel MOSFET shows α values of about 4×10−7 which are among the lowest values ever reported in literature. The α values in the surface channel devices are about two orders of magnitude higher than those in the bulk type. Comparing the d.c. characteristics and 1/f noise of both devices, an indication is given on how to reduce the 1/f noise in a surface p-channel MOSFET.

Parameter extraction and 1/f noise in a surface and a bulk-type p-channel LDD MOSFET

We report on contact effects in polymeric thin film transistors based on poly(3-octylthiophene) and poly(3-hexadecylthiophene) with gold contact electrodes and in the bottom contact configuration. A method to extract the intrinsic channel mobility from the measured extrinsic mobility over a broad range of gate voltage is presented. This method uses the I-V characteristics of the transistor in its reverse mode operation. The results show that the intrinsic mobility in the channel is gate voltage dependent and increases almost linearly with voltages at biases above the threshold voltage. By applying a model based on the theory of space-charge-limited conduction, the dependence of the threshold voltage on the contacts and the shifts observed in this parameter with different polymer film thicknesses are explained. We also apply this model to explain the effects of light in reducing the contact effects and changing the device parameters from extrinsic in the dark to intrinsic under illumination.

Contact effects and extraction of intrinsic parameters in poly(3-alkylthiophene) thin film field-effect transistors

A new method for measuring the threshold voltage of small geometry MOS devices is presented. Based on the drain current equation in the subthreshold region, the threshold voltage ( V TH ), defined as the gate voltage required for a surface band-bending of 2 φ F , can be accurately determined experimentally by the Quasi-Constant-Current (QCC) method. Compared with some other commonly used methods, this technique has the advantages of better fitting accuracy in subthreshold region, extracting the V TH with a unique value, and being suitable for small geometry devices over a wide range of voltage biases, temperatures, and process parameter variations. It can be used either for circuit simulation like the MOS3 model in SPICE, or as a routine monitor of processing like channel doping profile, gate oxide thickness or source and drain junction depths.

A new method for measuring the threshold voltage of small-geometry MOSFETs from subthreshold conduction

This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: (R) = δV TH (DIBL) δV DS = αL −β , α = α0 + α1VBS, β = β0 + β1VBS has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters α and β were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.

The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K

This paper presents detailed comparisons between the room temperature and liquid nitrogen temperature experimental and 2-D simulation DIBL results in varying channel lengths NMOS and PMOS devices. The results in PMOS devices showed that DIBL is always worse at 300 than at 77 K. However, for NMOS devices, a unique DIBL temperature-dependent feature was observed, that is, DIBL is improved for devices with L L > 1.2 μ m, but is worse for devices in which 0.6 L μ m. Investigation of the physical mechanisms for explaining the above phenomenon in both types of MOS devices was carried out with the new version of the 2-D device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures. The simulation results show that: (a) the major difference between NMOS and PMOS devices structure is the additional B-ion channel doping which tends to prevent punch-through in the sub-surface region for shorter channel NMOS devices, but forms a buried p -type sub-surface channel for shorter channel PMOS devices; and (b) lowering the temperature from 300 to 77 K caused the channel current path to be pushed back towards the channel surface for both NMOS and PMOS devices due to the freeze-out effect in the substrate. Therefore, the observed DIBL characteristics could be explained physically by the combination of the different source drain junction potential profiles between NMOS and PMOS devices, and the different current flow paths at 300 and 77 K.

Z.X. Yan

Papers

A new method for measuring the threshold voltage of small-geometry MOSFETs from subthreshold conduction

The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K

Comparison of drain-induced barrier-lowering in short-channel NMOS and PMOS devices at 77 K