Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Software engineering is concerned with the development and evolution of high-quality software systems in a systematic, controlled, and efficient manner. Software engineers are concerned with safety and reliability of the product as well as the cost and schedule of the development process. The lectures and the group projects will cover all aspects of the software life cycle, from development team management, problem specification and analysis, system design techniques, implementation and documentation practices, testing, to maintenance and evaluation of the final product.

Uml Distilled A Brief Guide To The Standard Object Modeling Language

How Many People Can the Earth Support? By Joel E. Cohen. Norton: 1995. Pp. 532. $30, £22.50. UK publication date, 27 March.

Book of numbers

In this paper, we present LearnLib, a library for active automata learning. The current, open-source version of LearnLib was completely rewritten from scratch, incorporating the lessons learned from the decade-spanning development process of the previous versions of LearnLib. Like its immediate predecessor, the open-source LearnLib is written in Java to enable a high degree of flexibility and extensibility, while at the same time providing a performance that allows for large-scale applications. Additionally, LearnLib provides facilities for visualizing the progress of learning algorithms in detail, thus complementing its applicability in research and industrial contexts with an educational aspect.
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https://link.springer.com/content/pdf/10.1007%2F978-3-319-21690-4_32.pdf

The Open-Source LearnLib

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bit stream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Fault tolerant system design and SEU injection based testing

Polymorphic gates are unconventional logic components which can switch their logic functions according to changing environment. The first part of this study presents an evolutionary approach to the design of polymorphic modules which exhibit different logic functions in different environments. The most complicated circuit that we evolved contains more than 100 gates. The second part of this study shows how to reduce the number of test vectors of a digital circuit by replacing some of its gates by polymorphic gates. In the first polymorphic mode, the circuit implements the original function. When switched to the second polymorphic mode, it can be tested using fewer test vectors than in the first polymorphic mode; however, the same fault coverage is obtained. The number of test vectors was reduced on 50-91% of its original volume for six benchmark circuits. The paper also discusses various obstacles which one has to deal with during a practical utilization of polymorphic gates.

Polymorphic Gates in Design and Test of Digital Circuits

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Zdenek Kotasek

Papers

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Fault tolerant system design and SEU injection based testing

Polymorphic Gates in Design and Test of Digital Circuits

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration