Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Contact metallization scheme using a barrier layer over a silicide layer

Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.

Electroless deposition process on a silicon contact

30years of electroless plating for semiconductor and polymer micro-systems

In this report, the hole-filling characteristics upon addition of SPS were evaluated in detail by cross-sectional scanning electron microscopy ~SEM!, and the effects of SPS concentration on bottom-up fill ability, and fundamental film properties such as contaminant level, crystal texture, and surface morphology were investigated. Experimental ICB-Pd layers with a thickness of 1 or 2 nm were deposited on the surface of three types of TaN/SiO2 /Si substrates, hole patterns ~diameter, 0.31-1.0 mm; depth, 1.5 mm! for investigating filling viahole; trench patterns ~length, 100 mm; width, 0.21-100 mm; depth, 0.3 mm! for electrical resistivity measurement; and blankets for measurement of the deposition rate of electroless plating with SPS concentration. The thickness of the Pd layer was determined by a quartz microbalance placed on the substrate surface. Prior to electroless copper plating, all substrates were cleaned by ultrasonication in acetone at room temperature for 10 min. The composition of the electroless copper plating solution was CuSO4 i 5H2O ~6.6 g/L! ,C 10H16N2O8 ~EDTA; 70.0 g/L!, glyoxylic acid ~18.0 g/L! as a reducing agent, 2,28-dipyridine ~0.04 g/L! as stabilizer, polyethylene glycol ~4000 MW, 0.5 g/L! as the surface activator. The pH of the plating bath was adjusted to approximately 12.5 using tetramethylammonium hydroxide ~TMAH! and the bath temperature was maintained at 70°C. The interfacial structure and morphology of samples were characterized by field-emission scanning electron microscopy~FE-SEM! and field-emission transmission electron microscopy~FE-TEM! .A ll SEM and TEM samples were prepared by focused ion beam ~FIB!. To protect the surface of the Cu film for etching during FIB cutting, a fine film of epoxy resin was coated on the surface of Cu by spin

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Bottom-Up Fill for Submicrometer Copper Via Holes of ULSIs by Electroless Plating

Bottom-up fill of Cu in deep submicrometer via holes was achieved through electroless plating alone for the first time. We investigated the effect of addition of inhibitor molecules to electroless Cu plating solution, and found that sulfopropyl sulfonate ~SPS! was highly effective in promoting the bottom-up fill. The tendency for bottom-up filling was enhanced by shrinkage of the hole diameter. This suggests that the diffusion flux of SPS molecules to the bottom of holes was more suppressed for smaller holes.

https://www.webpages.uidaho.edu/nanomaterials/research/Papers/Barriers/Ta/ECSSL%20Bottom%20up%20fill%20of%20copper%207(6)%20C78-C80%20(2004).pdf

Zengling Wang

Papers

Bottom-Up Fill of Copper in Deep Submicrometer Holes by Electroless Plating