Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Contact metallization scheme using a barrier layer over a silicide layer

Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.

Electroless deposition process on a silicon contact

Because of their unique electrical and optical properties, Si nanowires have attracted considerable attention, and already a number of devices based on Si nanowires as building blocks have been demonstrated. [1–4] Nanowires grown by using the vapor–liquid–solid (VLS) technique have been shown to have advantages compared with conventional lithographic techniques in terms of well-defined surface, small minimum size, and fabrication cost. Additionally, the VLS technique can be used to prepare epitaxially grown nanowires on single-crystal substrates. Vertically standing epitaxial nanowires as a device platform [3,4] avoid pick-and-place approaches or nanomanipulations. For vertical devices, control of growth direction and crystallographic orientation of the nanowire are important parameters. In order to combine vertically grown epitaxial Si nanowires with conventional Si micro/nanoelectronics manufactured on Si(100) wafers, the most important issue is the realization of vertically grown epitaxial Si nanowires, along the [100] direction, on Si(100) substrates. Epitaxial Si nanowires grown without any template on Si substrates reported up to now have three preferred growth directions, in particular , , and depending on the diameter of the wires. [5] Based on the present knowledge the preferred growth directions are for large diameter nanowires and and for small diameters, independent of the growth method, if no template is used. In this paper, we utilize an anodic aluminum oxide (AAO) template with vertical nanopores to grow epitaxial Si(100) nanowires on a Si(100) substrate. AAO is known to have ordered honeycomb nanopore arrays, perpendicular to the substrate. The diameter and the density of the nanopores can be controlled from a few nano

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Synthesis of Vertical High-Density Epitaxial Si(100) Nanowire Arrays on a Si(100) Substrate Using an Anodic Aluminum Oxide Template**

The low limit of the deposition temperature for atomic layer deposition (ALD) of noble metals has been studied. Two approaches were taken; using pure oxygen instead of air and using a noble metal starting surface instead of Al2O3. Platinum thin films were obtained by ALD from MeCpPtMe3 and pure oxygen at deposition temperature as low as 200 °C, which is significantly lower than the low-temperature limit of 300 °C previously reported for the platinum ALD process in which air was use da s the oxygen source. The platinum films grown in this study had smooth surfaces, adhered well to the substrate, and had low impurity contents. ALD of ruthenium, on the other hand, took place at lower deposition temperatures on an iridium seed layer than on an Al2O3 layer. On iridium surface, ruthenium films were obtained from RuCp2 and oxygen at 225 °C and from Ru(thd)3 and oxygen at 250 °C, whereas no films were obtained on Al2O3 at temperatures lower than 275 and 325 °C, respectively. The crystal orientation of the ruthenium films was found to depend on the precursor. ALD of palladium from a palladium -ketoiminate precursor and oxygen at 250 and 275 °C was also studied. However, the film-growth rate did not saturate to a constant level when the precursor pulse times were increased.

Atomic layer deposition of noble metals: Exploration of the low limit of the deposition temperature

Bottom-up fill of Cu in deep submicrometer via holes was achieved through electroless plating alone for the first time. We investigated the effect of addition of inhibitor molecules to electroless Cu plating solution, and found that sulfopropyl sulfonate ~SPS! was highly effective in promoting the bottom-up fill. The tendency for bottom-up filling was enhanced by shrinkage of the hole diameter. This suggests that the diffusion flux of SPS molecules to the bottom of holes was more suppressed for smaller holes.

https://www.webpages.uidaho.edu/nanomaterials/research/Papers/Barriers/Ta/ECSSL%20Bottom%20up%20fill%20of%20copper%207(6)%20C78-C80%20(2004).pdf

Bottom-Up Fill of Copper in Deep Submicrometer Holes by Electroless Plating

In this report, the hole-filling characteristics upon addition of SPS were evaluated in detail by cross-sectional scanning electron microscopy ~SEM!, and the effects of SPS concentration on bottom-up fill ability, and fundamental film properties such as contaminant level, crystal texture, and surface morphology were investigated. Experimental ICB-Pd layers with a thickness of 1 or 2 nm were deposited on the surface of three types of TaN/SiO2 /Si substrates, hole patterns ~diameter, 0.31-1.0 mm; depth, 1.5 mm! for investigating filling viahole; trench patterns ~length, 100 mm; width, 0.21-100 mm; depth, 0.3 mm! for electrical resistivity measurement; and blankets for measurement of the deposition rate of electroless plating with SPS concentration. The thickness of the Pd layer was determined by a quartz microbalance placed on the substrate surface. Prior to electroless copper plating, all substrates were cleaned by ultrasonication in acetone at room temperature for 10 min. The composition of the electroless copper plating solution was CuSO4 i 5H2O ~6.6 g/L! ,C 10H16N2O8 ~EDTA; 70.0 g/L!, glyoxylic acid ~18.0 g/L! as a reducing agent, 2,28-dipyridine ~0.04 g/L! as stabilizer, polyethylene glycol ~4000 MW, 0.5 g/L! as the surface activator. The pH of the plating bath was adjusted to approximately 12.5 using tetramethylammonium hydroxide ~TMAH! and the bath temperature was maintained at 70°C. The interfacial structure and morphology of samples were characterized by field-emission scanning electron microscopy~FE-SEM! and field-emission transmission electron microscopy~FE-TEM! .A ll SEM and TEM samples were prepared by focused ion beam ~FIB!. To protect the surface of the Cu film for etching during FIB cutting, a fine film of epoxy resin was coated on the surface of Cu by spin

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Bottom-Up Fill for Submicrometer Copper Via Holes of ULSIs by Electroless Plating

Electroless plated copper can be deposited on a TaN surface initiated by displacement plating when the surface oxide layer is removed by wet chemical etching. For application to ultra-large-scale integrated (ULSI) interconnection technology in which very thin TaN barrier films are used, it is essential to form a stable TaN film with minimal native oxide thickness. In this study, TaN films with various N/Ta atomic ratios were fabricated by reactive sputtering and native oxide growth on the surface was investigated by x-ray photoelectron spectroscopy, high resolution Rutherford backscattering spectrometry, and x-ray diffraction (XRD). It was found that when the N/Ta atomic ratio in the film was lower than 1.2, surface oxidation of the TaN film advanced with time. When the ratio was higher than 1.2, oxidation of the TaN film stopped at 1 ML. The XRD spectra indicated that when the N/Ta atomic ratio was between 0.82 and 1.25, face-centered-cubic TaN films were formed and the resistivity increased with an increase in the N/Ta ratio. Thus, a TaN film with a N/Ta ratio of 1.25 ratifies the minimal surface oxide thickness as well as low-resistivity requirements, and is appropriate for ULSI Cu interconnections using electroless Cu deposition.

Suppression of native oxide growth in sputtered TaN films and its application to Cu electroless plating

The effects of additives, such as Cl-, thiourea, benzotriazole, bis(3-sulfopropyl)-disulfide (SPS), and mercaptonicotinic acid, upon the hole filling characteristic of electroless Cu plating were investigated. With the addition of thiourea, the Cu deposition rate was suppressed and the hole filling characteristic became anti-bottom-up filling with the presence of voids. With the addition of SPS, bottom-up Cu filling was achieved and the bottom-up tendency increased with an increase in SPS concentration. The mechanism of anti-bottom-up filling and bottom-up filling with the addition of thiourea or SPS is attributed to the diffusion flux of thiourea being higher than that of Cu2+-EDTA complex, and the diffusion flux of SPS being lower than that of Cu2+-EDTA complex.

Effect of Additives on Hole Filling Characteristics of Electroless Copper Plating

A continuous electroless-plated Cu film of only 10 nm in thickness was successfully deposited on a TaN barrier over a 1 nm-thick Pd catalytic layer formed by ionized cluster beam deposition. The electrical resistivity of the Cu interconnection was found to decrease as the Pd layer thickness was reduced, to as low as 2.1 µΩcm at a Pd thickness of 1 nm. Moreover, the deposited film has adhesion strength as high as that of sputtered Cu on TaN, even for the case of the 1 nm-thick Pd catalyst layer. A uniform and continuous 10 nm-thick Cu seed layer was formed by electroless plating over a 1 nm-thick Pd layer, and subsequent Cu electroplating filled all high aspect ratio via-holes without the appearance of voids.

Osamu Yaegashi

Papers

Bottom-Up Fill of Copper in Deep Submicrometer Holes by Electroless Plating

Bottom-Up Fill for Submicrometer Copper Via Holes of ULSIs by Electroless Plating

Suppression of native oxide growth in sputtered TaN films and its application to Cu electroless plating

Effect of Additives on Hole Filling Characteristics of Electroless Copper Plating

Highly Adhesive Electroless Cu Layer Formation Using an Ultra Thin Ionized Cluster Beam (ICB)-Pd Catalytic Layer for Sub-100 nm Cu Interconnections