Microwave signal filtering is a fundamental and central functionality in radio-frequency (RF) systems. Underpinned by advanced integrated photonics technologies, emerging integrated microwave photonic (IMWP) filter platforms enable reconfigurable and widely tunable RF signal filtering functionalities that were unattainable using conventional electronics while also exhibiting superior features in terms of compactness, light weight, stability, low power consumption, and low latency. This paper presents a comprehensive review of the principles, architectures, and performance of IMWP filters. We highlight recent advances of IMWP filters enabled by on-chip nonlinear optics, RF-interference technology and emerging integration platforms, with an emphasis on the RF performance which is critical for their usability in real-world applications. We conclude with a perspective on future research challenges and new possibilities for IMWP filters.

Integrated microwave photonic filters

This paper presents a $64 \times 2$ channel stereo-audio sensing front end with parallel asynchronous event output inspired by the biological cochlea. Each binaural channel performs feature extraction by analog bandpass filtering, and the filtered signal is encoded into events via asynchronous delta modulation (ADM). The channel central frequencies $f_{0}$ are geometrically scaled across the human hearing range. Two design techniques are highlighted to achieve the high system power efficiency: source-follower-based bandpass filters (BPFs) and asynchronous delta modulation (ADM) with adaptive self-oscillating comparison. The chip was fabricated in 0.18 $\mu \text{m}$ 1P6M CMOS, and occupies an area of $10.5 \times 4.8$ mm2. The core cochlea system operating under a 0.5 V power supply consumes 55 $\mu \text{W}$ at an output rate of 100k event/s. The measured range of $f_{0}$ is from 8 Hz to 20 kHz, and the BPF quality factor ${Q}$ can be tuned from 1 to almost 40. The 1 $\sigma $ mismatch of $f_{0}$ and ${Q}$ between two ears is 3.3% and 15%, respectively, across all channels at ${Q}\approx $ 10. Reconstruction of speech input from the event output of the chip is performed to validate the information integrity in event-domain representation, and vowel discrimination is demonstrated as a simple application using histograms of the output events. This type of silicon cochlea front end targets integration with embedded event-driven processors for low-power smart audio sensing with classification capabilities, such as voice activity detection and speaker identification.

A 0.5 V 55 $\mu \text{W}$ 64 $\times $ 2 Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing

This paper presents an ultra-low-power voice activity detector (VAD). It uses analog signal processing for acoustic feature extraction (AFE) directly on the microphone output, approximate event-driven analog-to-digital conversion (ED-ADC), and digital deep neural network (DNN) for speech/non-speech classification. New circuits, including the low-noise amplifier, bandpass filter, and full-wave rectifier contribute to the more than 9 $\times $ normalized power/channel reduction in the feature extraction front-end compared to the best prior art. The digital DNN is a three-hidden-layer binarized multilayer perceptron (MLP) with a 2-neuron output layer and a 48-neuron input layer that receives parallel event streams from the ED-ADCs. To obtain the DNN weights via off-line training, a customized front-end model written in python is constructed to accelerate feature generation in software emulation, and the model parameters are extracted from Spectre simulations. The chip, fabricated in 0.18- $\mu \text{m}$ CMOS, has a core area of 1.66 $\times $ 1.52 mm2 and consumes 1 $\mu \text{W}$ . The classification measurements using the 1-hour 10-dB signal-to-noise ratio audio with restaurant background noise show a mean speech/non-speech hit rate of 84.4%/85.4% with a 1.88%/4.65% 1- $\sigma $ variation across ten dies that are all loaded with the same weights.

Design of an Always-On Deep Neural Network-Based 1- $\mu$ W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

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Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

In this paper, a variation-aware and reliable design of a fully integrated radio frequency (RF) bandpass filter realized using a voltage differencing transconductance amplifier is presented. The filter is characterized by its high frequency operation, low power consumption, high quality factor, and it is insensitive to process, voltage, and temperature variations. Sensitivity analysis has been performed to analyze the circuit performance in the presence of parasitics. The inductor-less approach finds its application in integrated building blocks of RF front ends, thus eliminating the requirement of off-chip filters in transceivers. Centered at 2.511 GHz and operating within the 36.21 MHz 3-dB bandwidth, the filter draws 0.168 mA from a ±1 V power supply, attains a voltage gain of 72.6 dB, a quality factor of 69.34 and noise figure of ~29.6 dB. In addition, it has a dynamic range of 125.84 dB-Hz and a 1-dB compression of −1.5 dBm which translates into a figure of merit as high as 94 dB.

A 2.5 GHz Low Power, High- ${Q}$ , Reliable Design of Active Bandpass Filter

In this paper, design techniques for an integrated RF bandpass filter are discussed. A novel wide-tuning high-Q active bandpass filter utilizing the active inductors is presented. Issues of the active inductor related to Q -enhancement, noise, linearity, and stability are considered. The circuit has been fabricated in an 0.18-mum CMOS process, and the filter occupies the active area of 150 times 200 mum2. Measurement results show that the filter centered at 3.82 GHz with about 36-MHz bandwidth (3-dB) is tunable in frequency from about 1.92 to 3.82 GHz, and it exhibits -15- to 1-dB compression point at 2.44 GHz with approximately 60-MHz bandwidth while the dc power consumes 10.8 mW.

A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends

In this paper, a full CMOS six-order Gm-C Chebyshev filter based on passive LC-ladder synthesis is designed in TSMC standard 0.25mum CMOS process, which uses a highly linear operational transconductance amplifier (OTA) based on cross-coupled differential pairs, which exhibits a wide product of gain and bandwidth. A common-mode feedback (CMFB) with improved stability is introduced. The simulated results show the center frequency tuning range of the filter is from about 1.5MHz to 11 MHz and the maximum quality factor of 150 at the center frequency 6MHz. The filter is suitable for multi-band wireless applications

A High Q Gm-C Filter for Multi-band Wireless Applications

Efficient 1D and 2D mixed motion estimation array architectures for MPEG-4 AS profile video encoding are presented in this paper To reduce the utilization of the global bus to the external memory and to improve the computation efficiency of the array, a novel local memory scheme and an improved 2D systolic array architecture for 16/spl times/16 macroblock motion estimation are proposed For 8/spl times/8 block motion estimation, a 1D broadcast array architecture is also presented The motion estimation processor is implemented using TSMC 025 /spl mu/m 1-poly 5-metal CMOS technology, which occupies a silicon area of 319/spl times/319mm/sup 2/ Experimental results show that it is able to estimate texture motion vectors of MPEG-4 AS profile in ITU-R601 format (720/spl times/576 at 25 Hz/PAL) in real-time at around 937 MHz

VLSI implementation of full pixel motion estimation processor for MPEG-4 AS profile

In this paper, the reconfigurable principle of N-path filter structure is presented, and the transfer function of N-path bandpass filter is given. Then based on SMIC 55nm CMOS process, a reconfigurable N-path filter is designed. On the basis of the tunable center frequency of the restructured N-path filter, the filter can also realize the functions of band-pass filter, notch filter and low-pass filter by configuring it.

Zhi-Qiang Gao

Papers

A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends

A High Q Gm-C Filter for Multi-band Wireless Applications

VLSI implementation of full pixel motion estimation processor for MPEG-4 AS profile

Design of the Reconfigurable N-path Filter