A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) and by both $\Delta {V}_{\text {T}}$ and subthreshold slope shift ( $\Delta $ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring $\Delta $ SS on OFF current and static power ( ${P}_{\text {static}}$ ) is estimated.

A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

As a general and rigid mathematical tool, wavelet theory has found many applications and is constantly developing. This article reviews the development history of wavelet theory, from the construction method to the discussion of wavelet properties. Then it focuses on the design and expansion of wavelet transform. The main models and algorithms of wavelet transform are discussed. The construction of rational wavelet transform (RWT) is provided by examples emphasizing the advantages of RWT over traditional wavelet transform through a review of the literature. The combination of wavelet theory and neural networks is one of the key points of the review. The review covers the evolution of Wavelet Neural Network (WNN), the system architecture and algorithm implementation. The review of the literature indicates the advantages and a clear trend of fast development in WNN that can be combined with existing neural network algorithms. This article also introduces the categories of wavelet-based applications. The advantages of wavelet analysis are summarized in terms of application scenarios with a comparison of results. Through the review, new research challenges and gaps have been clarified, which will serve as a guide for potential wavelet-based applications and new system designs.

https://ieeexplore.ieee.org/ielx7/6287639/6514899/09785993.pdf

A Review of Wavelet Analysis and Its Applications: Challenges and Opportunities

As a general and rigid mathematical tool, wavelet theory has found many applications and is constantly developing. This article reviews the development history of wavelet theory, from the construction method to the discussion of wavelet properties. Then it focuses on the design and expansion of wavelet transform. The main models and algorithms of wavelet transform are discussed. The construction of rational wavelet transform (RWT) is provided by examples emphasizing the advantages of RWT over traditional wavelet transform through a review of the literature. The combination of wavelet theory and neural networks is one of the key points of the review. The review covers the evolution of Wavelet Neural Network (WNN), the system architecture and algorithm implementation. The review of the literature indicates the advantages and a clear trend of fast development inWNNthat can be combined with existing neural network algorithms. This article also introduces the categories of wavelet-based applications. The advantages of wavelet analysis are summarized in terms of application scenarios with a comparison of results. Through the review, new research challenges and gaps have been clarified, which will serve as a guide for potential wavelet-based applications and new system designs. 

Estimating the aging-related degradation and failure of nanoscale integrated circuits (ICs), before they actually occur, is crucial for developing aging prevention/mitigation actions and in turn avoiding unexpected in-field circuit failures. Real-time monitoring of IC operating conditions can be efficiently used for predicting aging degradation and in turn timing failures caused by device aging. The existing approaches only take some specific operating conditions (e.g., workload or temperature) into account. In this paper, we propose a novel method for real-time IC aging prediction by extending the prediction schemes to a comprehensive model which takes into account any time-variant dynamic operating conditions relevant to aging prediction. Using a machine learning prediction model and the notion of equivalent aging time, we show that our approach outperforms the existing methods in terms of aging-prediction accuracy under different scenarios of time-variant operating conditions.

Real-Time Prediction for IC Aging Based on Machine Learning

This article proposes a condition monitoring scheme for the dc-link capacitors used in ac/dc/ac pulsewidth-modulation converters based on the signal injection, which can estimate capacitance in real time when both the rectifier and the inverter are in normal operation. First, a low-frequency signal is injected into the dc-link voltage, and its effects on the total harmonic distortion (THD) of the input current are analyzed. Accordingly, a suitable injection frequency is selected to keep the THD of input current within limits prescribed by the IEEE standard. Then, a novel calculation method of capacitor current without any dc-link current sensor is given, where the converter system is still in normal operation and different inverter operations are both taken into consideration. Finally, capacitance estimation based on the slide discrete Fourier transform is introduced. At the end of this article, experiments have been done to validate the correctness of the conclusion and effectiveness of the proposed scheme.

Online Condition Monitoring of DC-Link Capacitor for AC/DC/AC PWM Converter

The aluminum electrolytic capacitor (AEC) is one of the most important parts of a power electronic converter. Throughout its lifespan, the equivalent series resistance (ESR) of the AEC will increase, which will affect the performance of the power electronic converter. To guarantee the reliability of a converter, it is necessary to monitor the health state of the AEC, for which one common technique is to estimate the ESR of the AEC. Equipment with a high sampling rate is usually required because converter usually works at a high frequency. This requirement will increase the cost of ESR monitoring. To address this issue, this article proposes a novel method of estimating the ESR for an AEC. The proposed method uses an innovative compressed sensing approach to acquire the ripple voltage and current. Instead of complete reconstruction of the ripple voltage and current, only the high-frequency features in the wavelet subspace are reconstructed and used to calculate the ESR. The proposed method reduces the cost of data sampling, transmission, and storage. This method is not limited by the converter circuit structure and can be applied in various environments. Simulations and experiments were carried out to verify the effectiveness of the proposed method.

ESR Estimation for Aluminum Electrolytic Capacitor of Power Electronic Converter Based on Compressed Sensing and Wavelet Transform

The invention relates to an improved scan chain unit and a non-concurrent testing method based on the same, which belongs to the filed of on-chip system testing and aims at solving the problems that the existing scan chain-based non-concurrent on-line testing method has strict requirements for time sequences, is difficult to control and can not realize the one-step import of multiple groups of test vectors The improved scan chain unit is used for replacing a D trigger in an on-chip system, and the unit contains two triggers and two selectors, wherein a first trigger is a basic unit which composes the original circuit scan chain and is used for realizing the function same with that of the original D trigger, and a second trigger is introduced for saving data in the testing process; and the two data selectors control the flow direction of data by means of enable ends, a first selector is used for controlling whether data in the second trigger can be transmitted to the first trigger, and a second selector is used for controlling the working state or the scanning state of the first trigger Thus, multiple groups of test vectors can be input to the unit for continuous testing, and therunning state of the circuit is not changed before and after the test

Improved scan chain unit and non-concurrent testing method based on same

The invention relates to an on-line error correcting device for faults by parity check codes and a method thereof, belonging to the field of on-line test. The invention solves the problem of huge redundant cost when traditional error correcting codes are used for the on-line test for an embedded memory. The on-line error correcting device for faults comprises two processes of error detection and error correction, wherein the error detection comprises the following steps of: detecting whether new addresses are input or read-write signals are changed; calculating check codes for data; reading the data and comparing the data with memorized check codes; writing a compared result in a fault flag bit memory; and respectively writing fault addresses and the error correcting codes in corresponding memories. The process of the error correction comprises the following steps of: detecting whether the new addresses are input or the read-write signals are changed; judging fault flag bits; and searching the error correcting codes. By using the invention, the on-line test is carried out for the embedded memory under the condition that the memories are not changed to memorize data and the normal read-write operation of the memories is not influenced, and all the faults of odd numbers are detected.

On-line error correcting device for fault by parity check code and method thereof

Supply voltage assignment (SVA) can alleviate the performance aging induced by the negative bias temperature instability (NBTI) effect However, due to the random characteristic of an actual system workload, it is difficult to estimate the aging rate and control the supply voltage reasonably To solve this problem, we present a workload-aware SVA method (WSVA) that encapsulates the workload change into the aging estimation using an LUT-based approach Moreover, an NBTI and leakage co-optimization strategy based on an integer linear programming (ILP) approach is proposed to obtain the optimal input vector in standby mode Simulation experiments on multiple benchmark circuits demonstrate that the LUT-based approach can track the dynamic change of the workload online and provide an accurate aging estimate for SVA with little computation cost Compared with the SVA method without considering the workload, the proposed aging estimation approach and the optimal input vector selection strategy in the WSVA framework can enable the CMOS circuit conserve additional power dissipation while guaranteeing the performance requirements

Zhiming Yang

Papers

ESR Estimation for Aluminum Electrolytic Capacitor of Power Electronic Converter Based on Compressed Sensing and Wavelet Transform

Improved scan chain unit and non-concurrent testing method based on same

On-line error correcting device for fault by parity check code and method thereof

NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

NBTI-aware adaptive minimum leakage vector selection using a linear programming approach