Showing papers in "Integration in 2016"

TL;DR: An IC market model is elaborate to illustrate the potential HT threats faced by the parties involved in the model and categorize the recent research advances in the countermeasures against HT attacks.

TL;DR: AIDA is presented, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description, and the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated.

TL;DR: Two novel ternary CNTFET-based SRAM cells are proposed in this paper; in nearly all cases, the proposed cells outperform existing CNTFets by showing a small standard deviation in the simulated memory circuits.

TL;DR: An extensive review of state-of-the-art design automation techniques for application-specific on-chip interconnects, including several advanced aspects such as co-synthesis of memory and communication architectures, joint scheduling and interconnect synthesis, floorplanning, dynamic configuration, multi-path communication.

TL;DR: In this paper, an ultra-wideband (UWB) CMOS low noise amplifier (LNA) utilizing an active inductor-based input matching network is presented.

TL;DR: An automatic synthesis of three typical blocks of nowadays RF front-end receivers, a narrowband differential low-noise amplifier, a mixer and a local oscillator, is presented, proving the surplus value of using an automatic IC design tool in RF circuitry synthesis.

TL;DR: It is found that direct-form structure involves significantly less registers than the transpose- form structure, and it allows register reuse in parallel implementation, which is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes.

TL;DR: A systematic survey on security risks in the VLSI supply chain and their corresponding mitigation techniques is presented.

TL;DR: By increasing the inductance value of the matching network in constant operating frequency, the PAE peak moves from high power to low power levels without any degradation, and it is possible to maintain the power efficiency at the same maximum level for lower input drive levels.

TL;DR: A new algorithm designed to solve floorplanning problems optimally which finds solutions to rectangle packing problems which globally minimize wirelength and avoid given sets of blocked regions is presented.

TL;DR: Several challenges should be addressed properly: the essential nature of the stochastic behavior of aging, the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others.

TL;DR: Self-rectifying behavior of the memristive device efficiently improves the read operation performance of large-scale selectorless cross-point arrays and provides a guideline for circuit designers to improve the performance of oxide-based resistive memory (RRAM) based cross- point arrays.

TL;DR: A balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure to boost the gain and reduce the noise figure (NF).

TL;DR: This paper provides a comprehensive introduction to and presents extensions for the hardware description language SyReC which allows for the specification and automatic synthesis of reversible circuits and proposes algorithms that optimize the resulting circuits with respect to different objectives.

TL;DR: In this article, the authors comment on the dual-rail asynchronous logic multi-level integration, the VLSI Journal 47 (2014) 148-159 by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multilevel decomposition, and physical implementation.

TL;DR: In this paper, a high performance HW accelerator is proposed to extract and refine the Interest Points from images, by accurately calculating the Difference-of-Gaussian and using refinement algorithms from the SIFT method.

TL;DR: A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth, which maximizes routing resources over obstacles and saves routing resources outside obstacles.

TL;DR: The concept of hierarchical multi-objective optimization is applied to analog integrated circuit placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce post-layout routing-induced parasitics of the circuit.

TL;DR: A new bit-parallel Montgomery multiplier for GF ( 2 m ) is presented, where the field is generated with an irreducible trinomial using squaring operations, and matches the Karatsuba multiplier.

TL;DR: Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure and the consideration of thermal stress variation results in a retarded EM induced degradation.

TL;DR: The exact equations on the amplitude and frequency is derived in the proposed method, and provides the condition which the oscillator passes from being linear to nonlinear.

TL;DR: Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity.

TL;DR: A spiking neural network (SNN) implemented in digital CMOS is constructed based on an indirect training algorithm that utilizes spike-timing dependent plasticity (STDP) and validated by using its outputs to control the motion of a virtual insect.

TL;DR: An innovative on-Chip bus transfer mode - the Advanced Encryption Standard (AES) state transfer (AS) and a performance evaluation methodology to estimate the transfer performance are proposed and effectively used in the design flow.

TL;DR: A Sub-mW differential Common-Gate Low Noise Amplifier for ZigBee standard that takes the advantage of shunt feedback and Dual Capacitive Cross Coupling to reduce power consumption and the bandwidth extension capacitors to support 2.4GHz ISM band.

TL;DR: An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced and shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP).

TL;DR: This paper mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process.

TL;DR: Dass Brexit auch Brexit bedeutet, scheint es legitim zu erwarten, dass die politische Realität weniger eindeutig sein wird and verschiedene Szenarien als Ergebnis des Referendums denkbar sind.

TL;DR: A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving and an optimized decoding schedule scheme is presented to reduction the performance loss caused by high parallelism.

TL;DR: The performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation and the reliability parameters are a function of the adder architectures.