Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

Area-efficient high-speed decoding schemes for turbo decoders

Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First, the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders up to 20%.

/pdf/frequency-spectrum-based-low-area-low-power-parallel-fir-3u5597bkp3.pdf

Frequency spectrum based low-area low-power parallel FIR filter design

Turbo codes are one of the most powerful error correcting codes. The VLSI implementation of Turbo codes for higher decoding speed requires use of parallel architectures. This paper explores the design spaces of both serial and parallel MAP decoders using graphical analysis. Several existing designs are compared, and three new parallel decoding schemes are presented.

Parallel Turbo decoding

Decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in digital filters are presented in this paper. The transfer function and/or the input is decorrelated such that fewer bits are required to represent the coefficients and inputs. Thus, the size of the arithmetic units in the filter is reduced, thereby reducing the power dissipation. The DECOR transform is suited for narrow-band filters because there is significant correlation between adjacent coefficients. Simulations with fixed coefficient filters indicate reduction in transition activity, ranging from 6% to 52% for filter bandwidths ranging from 0.30 /spl pi/ to 0.05 /spl pi/, respectively, (where /spl pi/ corresponds to half the sample rate). Simulations with adaptive filters indicate reduction in transition activity in the F-block, ranging from 12% to 38% for filter bandwidths ranging from 0.30 /spl pi/ to 0.05 /spl pi/, respectively. The DECOR transforms result in greater energy savings and over a larger bandwidth than existing methods.

/pdf/decorrelating-decor-transformations-for-low-power-digital-1l07kjwq5d.pdf

Decorrelating (DECOR) transformations for low-power digital filters

In this paper, two efficient approaches are proposed to improve the performance of soft-output Viterbi algorithm (SOVA)-based turbo decoders. In the first approach, an easily obtainable variable and a simple mapping function are used to compute a target scaling factor to normalize the extrinsic information output from turbo decoders. An extra coding gain of 0.5 dB can be obtained with additive white Gaussian noise channels. This approach does not introduce extra latency and the hardware overhead is negligible. In the second approach, an adaptive upper bound based on the channel reliability is set for computing the metric difference between competing paths. By combining the two approaches, we show that the new SOVA-based turbo decoders can approach maximum a posteriori probability (MAP)-based turbo decoders within 0.1 dB when the target bit-error rate (BER) is moderately low (e.g., for 1/2 rate codes). Following this, practical implementation issues are discussed and finite precision simulation results are provided. An area-efficient parallel decoding architecture is presented in this paper as an effective approach to design high-throughput turbo/SOVA decoders. With the efficient parallel architecture, multiple times throughput of a conventional serial decoder can be obtained by increasing the overall hardware by a small percentage. To resolve the problem of multiple memory accesses per cycle for the efficient parallel architecture, a novel two-level hierarchical interleaver architecture is proposed. Simulation results show that the proposed interleaver architecture performs as well as random interleavers, while requiring much less storage of random patterns.

Transactions Papers High Performance, High Throughput Turbo/SOVA Decoder Design

Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders ranging from 4% to 24% and an average reduction of about 10%. Furthermore, the power consumption of these filters is reduced by 14.8% on average and ranges from 10% to 20%.

Efficient parallel FIR filter implementations using frequency spectrum characteristics

Turbo codes invented in 1993 have become one of the important research topics in communication and coding societies since their performance is close to the theoretical limit. In terms of applications, Turbo codes have been decided to be used in 3rd generation W-CDMA systems in many countries. In such cost sensitive applications, design of low cost VLSI Turbo decoders is of great interest. 
This thesis considers various VLSI implementation issues of Turbo decoders and develops efficient approaches for improving decoder performance, interleaver design, adaptive decoding and high speed decoding of Turbo codes. 
For maximum a posterior probability (MAP)-based Turbo decoders, an efficient state metrics normalization scheme is proposed. The best quantization schemes are presented for various variables considering trade-offs between decoder performance and hardware complexity. We also develop a novel adaptive decoding approach, which achieves very high power-down efficiency with negligible hardware overhead. There is no performance degradation and no introduced latency. A low power Turbo decoder chip based on the serial decoding architecture is designed, which is probably the first Turbo decoder chip embedded with an efficient adaptive decoding function. 
For soft output Viterbi algorithm (SOVA)-based Turbo decoders, two VLSI applicable approaches are proposed to improve the performance of Turbo decoders. It is shown that an extra coding gain of 0.5 dB can be obtained with the proposed performance improving approaches. Specifically, we show that, with finite wordlength implementation, new SOVA-based Turbo decoders can achieve almost the same coding gain as MAP-based Turbo decoders in some applications. 
We develop an area-efficient two-level hierarchal interleaver architecture, which performs at least as well as random-like interleavers while significantly reducing area requirement in VLSI implementation. 
We also propose a new terminology, namely Turbo Decoding Metrics . This is probably the first time to make it possible to provide soft information about decoded results instead of hard decision with CRC. Various application of TDMs are presented. 
We develop a class of area-efficient high speed Turbo decoding schemes. A modified version of the partial storage of state metrics approach is presented and it is shown that the new approach would achieve a better trade-off in most practical applications. Two types of pipelined parallel decoding schemes are developed. The usefulness of hybrid parallel decoding schemes is pointed out. The application of pipeline interleaving to parallel Turbo decoding architectures is presented.

Zhongfeng Wang

Papers

Transactions Papers High Performance, High Throughput Turbo/SOVA Decoder Design

Efficient parallel FIR filter implementations using frequency spectrum characteristics

High-performance, low-complexity vlsi design in turbo decoders