Proceedings of world academy of science, engineering and technology, vol 8

By utilizing a differential tunable active inductor for the LC-tank, a wide tuning-range CMOS voltage-controlled oscillator (VCO) is presented. In the proposed circuit topology, the coarse frequency tuning is achieved by the tunable active inductor, while the fine tuning is controlled by the varactor. Using a 0.18-mum CMOS process, a prototype VCO is implemented for demonstration. The fabricated circuit provides an output frequency from 500 MHz to 3.0 GHz, resulting in a tuning range of 143% at radio frequencies. The measured phase noise is from -101 to -118 dBc/Hz at a 1-MHz offset within the entire frequency range. Due to the absence of the spiral inductors, the fully integrated VCO occupies an active area of 150times300 mum2

A Wide Tuning-Range CMOS VCO With a Differential Tunable Active Inductor

Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First, the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders up to 20%.

/pdf/frequency-spectrum-based-low-area-low-power-parallel-fir-3u5597bkp3.pdf

Frequency spectrum based low-area low-power parallel FIR filter design

Decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in digital filters are presented in this paper. The transfer function and/or the input is decorrelated such that fewer bits are required to represent the coefficients and inputs. Thus, the size of the arithmetic units in the filter is reduced, thereby reducing the power dissipation. The DECOR transform is suited for narrow-band filters because there is significant correlation between adjacent coefficients. Simulations with fixed coefficient filters indicate reduction in transition activity, ranging from 6% to 52% for filter bandwidths ranging from 0.30 /spl pi/ to 0.05 /spl pi/, respectively, (where /spl pi/ corresponds to half the sample rate). Simulations with adaptive filters indicate reduction in transition activity in the F-block, ranging from 12% to 38% for filter bandwidths ranging from 0.30 /spl pi/ to 0.05 /spl pi/, respectively. The DECOR transforms result in greater energy savings and over a larger bandwidth than existing methods.

/pdf/decorrelating-decor-transformations-for-low-power-digital-1l07kjwq5d.pdf

Decorrelating (DECOR) transformations for low-power digital filters

A 4.8-GHz LC voltage-controlled oscillator (VCO) optimized for maximum tuning range was designed and fabricated using 0.25-/spl mu/m 1P5M CMOS process. The optimized design used an inverse proportionality between the two parasitic capacitances of the inductor and the MOS transistors for minimizing the parasitic capacitance at the oscillation node. The fabricated LC VCO has a wide tuning range of 20.3% from 4.32 GHz to 5.3 GHz with a power dissipation of 7.3 mW. This tuning range performance is comparable to, or better than, those of the reported CMOS LC VCOs in 5-GHz band. The measured phase noise is -82 dBc/Hz and -114.6 dBc/Hz at 100 KHz and 1-MHz offset, respectively.

5-GHz CMOS LC VCOs with wide tuning ranges

Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders ranging from 4% to 24% and an average reduction of about 10%. Furthermore, the power consumption of these filters is reduced by 14.8% on average and ranges from 10% to 20%.

Efficient parallel FIR filter implementations using frequency spectrum characteristics

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35- m CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver. Index Terms—Synchronous, stacked, driver, buck, converter, low voltage

http://www.koreascience.or.kr:80/article/JAKO201220962915926.pdf

An Optimized Stacked Driver for Synchronous Buck Converter

A CMOS bandgap reference voltage generator with reduced voltage variation and BJT area

delay time of DWA(Data Weighted Averaging) used in sigma-delta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigma-delta modulator improves the timing margin about 16%. The sub-circuits of sigma-delta modulator such as SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and DWA are designed with the non-ideal characteristics taken into account. The sigma-delta modulator has a maximum SNR (Signal to Noise Ratio) of 84 dB or 13 bit resolution.

Hang-Geun Jeong

Papers

5-GHz CMOS LC VCOs with wide tuning ranges

Efficient parallel FIR filter implementations using frequency spectrum characteristics

An Optimized Stacked Driver for Synchronous Buck Converter

A CMOS bandgap reference voltage generator with reduced voltage variation and BJT area

A 3rd order 3bit Sigma-Delta Modulator with Reduced Delay Time of Data Weighted Averaging