A comprehensive review of virtual synchronous generator

Remaining useful lifetime prediction and extension of Si power devices have been studied extensively. Silicon carbide (SiC) power devices have been developed and commercialized. Specifically, SiC mosfet s have been utilized for the next generation high-voltage, high-power converters with smaller size and higher efficiency, covering various mainstream applications, including photovoltaic systems, electric vehicles, solid-state transformers, and more electric ships and airplanes. However, the SiC-based devices have different failure modes and mechanisms compared with Si counterparts. Therefore, a comprehensive review is critical to develop accurate lifetime prediction and extension strategies for SiC power converter systems. The SiC power device component-level failure modes and mechanisms are first investigated. Different accelerated lifetime tests and component-level lifetime models are then compared. Power converter system-level offline lifetime modeling techniques and software tools are further summarized. Besides, the SiC power converter condition monitoring strategies and health indicators are surveyed. The online measurement challenges are also studied. Furthermore, the system-level lifetime extension strategies are reviewed. By integrating device physics, statistical modeling, reliability engineering, and mechanical engineering with power electronics, this article is intended to provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension.

Overview of Real-Time Lifetime Prediction and Extension for SiC Power Converters

Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high $dv/dt$ and $di/dt$ can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then, a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10-kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs, including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

A Review of Switching Slew Rate Control for Silicon Carbide Devices Using Active Gate Drivers

SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.0587

Review and analysis of SiC MOSFETs’ ruggedness and reliability

Compared with full-SiC mosfet s converters, the hybrid utilization of Si/SiC converters is an alternative approach to achieve the tradeoff between performance and cost. A systematic method is proposed to generate 2-SiC and 4-SiC hybrid three-level active neutral-point-clamped (3L-ANPC) inverter topologies from two types of switching cells based on the arrangement of freewheeling paths. The 2-SiC hybrid 3L-APNC inverter and the 4-SiC hybrid 3L-ANPC inverter are analyzed in detail with switching states and modulation strategies given. The power losses are quantitatively compared between the 2-SiC hybrid 3L-ANPC inverter and the 4-SiC hybrid 3L-ANPC inverter. The junction operating temperatures of active switches in different hybrid 3L-ANPC inverters are also estimated. With the same specifications and switching device parameters, the maximum output power of the 4-SiC hybrid 3L-ANPC inverter with modulation strategy I is almost 1.47 times than that of the 2-SiC hybrid 3L-ANPC inverter. A universal prototype for the full-SiC scheme, the full-IGBT scheme, and different Si/SiC hybrid schemes is built to evaluate these topologies at conversion efficiency and thermal characteristics. Experimental results and analysis show that the full-SiC 3L-ANPC inverter has the highest efficiency, whereas the 2-SiC hybrid 3L-ANPC inverter has the best cost performance. Further, the 4-SiC hybrid 3L-ANPC inverter with modulation strategy I has better thermal balance characteristic than that of the 2-SiC hybrid 3L-ANPC inverter, which shows significant superiority in high power density applications.

Evaluation of Different Si/SiC Hybrid Three-Level Active NPC Inverters for High Power Density

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

The hybrid switch (HyS) of a higher-current main Si IGBT and a parallel lower-current auxiliary Silicon Carbide (SiC) mosfet offer an improved cost/performance tradeoff for practical power electronic designs. The purpose of this paper is to investigate the short-circuit (SC) ruggedness, failure mechanisms, and techniques for improvement of the Silicon/SiC HyS. The influence of major limiting factors, including dc bus voltage, gate drive voltage, gate control pattern, case temperature, and SiC mosfet sizing are experimentally studied. Two SC failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC mosfet are identified using microscopic failure analysis techniques. An optimum gate control selection is proposed to improve the HyS's SC withstanding time with minimum increase in its power loss.

Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch

Si/SiC hybrid switches of parallel Si insulated-gate bipolar transistor (IGBT) and SiC metal–oxide–semiconductor field-effect transistor ( mosfet ) offer most of the SiC benefits but at a much lower cost in comparison to a full SiC solution. The hybrid switch can be optimized to achieve a minimum total power loss while utilizing the smallest SiC chip size without exceeding the specified maximum junction temperature. In this article, we first develop a generalized power loss model for Si/SiC hybrid switches with total power loss and junction temperature as outputs and SiC device size as a continuous input variable, and then develop a methodology to minimize SiC device size while optimizing total IGBT/ mosfet power loss and ensuring maximum junction temperature still below 150 °C. The power loss model is experimentally validated through both simple double pulse testing and a dc–dc buck converter case study. Using the model and optimization methodology, a minimum SiC device size can be obtained with optimized power loss and safe operation temperature.

Power Loss Model and Device Sizing Optimization of Si/SiC Hybrid Switches

Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

/pdf/active-gate-delay-time-control-of-si-sic-hybrid-switch-for-23s4ngaw4o.pdf

Zongjian Li

Papers

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch

Power Loss Model and Device Sizing Optimization of Si/SiC Hybrid Switches

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

Active Gate Delay Time Control of Si/SiC Hybrid Switch for Junction Temperature Balance Over a Wide Power Range