Showing papers by "Actel published in 2005"

Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array

Abstract: A field-programmable gate array (FPGA) having an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of the row driver line of each at least one row of RAM memory cells. A monitoring memory cell is coupled to a row driver line. Each monitoring memory cell is also coupled to a memory writing line. An FPGA also has RAM memory cells that act as the programming mechanism. The FPGA further has erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA. The FPGA is erased by providing at least one monitoring memory cell coupled to the erase circuitry. A memory clear phase is initiated on at least one monitoring memory cell. The monitoring memory cell then indicts the cell has been cleared.

Accelerating FPGA routing using architecture-adaptive A* techniques

Abstract: The A* algorithm is a well-known path-finding technique that is used to speed up FPGA routing. Previously published A*-based techniques are either targeted to a class of architecturally similar devices, or require prohibitive amounts of memory to preserve architecture adaptability. This work presents architecture-adaptive A* techniques that require significantly less memory than previously published work. Our techniques are able to produce routing runtimes that are within 7% (on an island-style architecture) and 9% better (on a hierarchical architecture) than targeted heuristic techniques. Memory improvements range between 30/spl times/ (island-style) and 140/spl times/ (hierarchical architecture).

Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material

Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

Face-to-face bonded I/O circuit die and functional logic circuit die system

Abstract: An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to­face bonding pads of each member of the other set.

Deglitching circuits for a radiation-hardened static random access memory based programmable architecture

Abstract: The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.

Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or TaN barrier metal layer

Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. An antifuse material layer comprising amorphous carbon is disposed above the upper surface of the tungsten plug. The antifuse material layer is disposed between adhesion-promoting layers. A layer of a barrier metal, consisting of either tantalum or tantalum nitride, is disposed over the antifuse layer to form an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse.

Dedicated input/output first in/first out module for a field programmable gate array

Abstract: A field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory. The dedicated input/output first-in/first-out memory comprising a plurality of input/output clusters coupled to the input/output pads of the field programmable gate array and a plurality of input/output block controllers coupled to said input/output clusters.

Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA

Abstract: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores, configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

Programming method for non-volatile memory and non-volatile memory-based programmable logic device

Abstract: A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

Voltage-and temperature-compensated rc oscillator circuit

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

A high-performance processor for embedded real-time control

Abstract: This brief reports on an algorithm and corresponding processor architecture for the construction of high-performance processors targeted at linear time invariant (LTI) control. The overall approach involves reformulating the controller into a particular discrete state-space representation, which is optimized for numerical efficiency using the /spl delta/ operator, then programming this into a specially-designed control system processor (CSP) implemented using a "programmable ASIC" device. This architecture presents large cost and performance benefits for control applications over traditional architectures, particularly for large multiple-input-multiple-output (MIMO) controllers. Results of implementing control of the vertical modes of a Maglev vehicle are presented and compared with implementations using commercial processors.

Bit line pre-settlement circuit and method for flash memory sensing scheme

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Volatile data storage in a non-volatile memory cell array

Abstract: A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

Integrated circuit wafer with inter-die metal interconnect lines traversing scribe-line boundaries

Abstract: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.

Esd protection structure for i/o pad subject to both positive and negative voltages

Abstract: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.

A 2.45 GHz wide tuning range VCO using MOS varactor in 0.35 /spl mu/m SiGe BiCMOS technology

Abstract: A full monolithic low-phase-noise wide-tuning-range voltage-control-oscillator (VCO) designed for a dual-band homodyne transceiver for WLAN applications is presented in this paper. The circuit is designed and implemented in a commercial 0.35 SiGe BiCMOS process. MOS varactor is used to realize a wide tuning range. Measured VCO circuit specifications feature a 440 MHz tuning range around 2.45 GHz, phase noise of -110 dBc/Hz at 1 MHz offset and -106 dBc/Hz at 600 KHz, out power of 7.68 dBm and power dissipation of 6.8 mA with 3 V supplies

Method for secure delivery of configuration data for a programmable logic device

Abstract: Secure delivery of configuration data of an intellectual property (IP) core includes the steps of loading configuration data for the IP core into IP core space by an IP core provider, masking portions of the IP core space not loaded with configuration data in the loading configuration data step with the value 0 or 1 by the IP core provider, encrypting data in the IP core space by the IP core provider, loading configuration data for system design other than for the IP core into a remainder space and any unused portions of the IP core space by a system designer, masking portions of the IP core space loaded in the loading configuration data step with the value 0 or 1 used by the IP core provider in the masking portions of the IP core space not loaded step, and encrypting data in a configuration space by the system designer.

Analysis of Successive Focused Ion Beam Slices by Scanning Electron Imaging and 3D Reconstruction

Abstract: An antifuse structure was analyzed using scanning electron microscope imaging and focused ion beam image slicing to generate a form of three-dimensional microscopy. This method reveals nanometer scale features that could not be easily imaged using a single focused ion beam cross-section. A novel end-point detection technique has been developed to control the thickness of the slice to about 2 nm. Voxel imaging and interpretive three-dimensional reconstruction was used to resolve volumes as small as 2 cubic nm3. It was determined that the fusing region for an antifuse is a complex mixture of material phases with an elliptical volume approximately 75 nm in diameter.

Apparatus and method for reducing leakage of unused buffers in an integrated circuit

Abstract: A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than V CC present on it.

Architecture for face-to-face bonding between substrate and multiple daughter chips

Abstract: An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.

Multi-level routing architecture in a field programmable gate array having transmitters and receivers

Abstract: A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

Delay locked loop for and FPGA architecture

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Method for using a chip carrier substrate with a land grid array and external bond terminals

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.