Showing papers by "Codex Corporation published in 1985"

Adaptive equalization

Abstract: Bandwidth-efficient data transmission over telephone and radio channels is made possible by the use of adaptive equalization to compensate for the time dispersion introduced by the channel Spurred by practical applications, a steady research effort over the last two decades has produced a rich body of literature in adaptive equalization and the related more general fields of reception of digital signals, adaptive filtering, and system identification. This tutorial paper gives an overview of the current state of the art in adaptive equalization. In the first part of the paper, the problem of intersymbol interference (ISI) and the basic concept of transversal equalizers are introduced followed by a simplified description of some practical adaptive equalizer structures and their properties. Related applications of adaptive filters and implementation approaches are discussed. Linear and nonlinear receiver structures, their steady-state performance and sensitivity to timing phase are presented in some depth in the next part. It is shown that a fractionally spaced equalizer can serve as the optimum receive filter for any receiver. Decision-feedback equalization, decision-aided ISI cancellation, and adaptive filtering for maximum-likelihood sequence estimation are presented in a common framework. The next two parts of the paper are devoted to a discussion of the convergence and steady-state properties of least mean-square (LMS) adaptation algorithms, including digital precision considerations, and three classes of rapidly converging adaptive equalization algorithms: namely, orthogonalized LMS, periodic or cyclic, and recursive least squares algorithms. An attempt is made throughout the paper to describe important principles and results in a heuristic manner, without formal proofs, using simple mathematical notation where possible.

Adaptive Lattice Decision-Feedback Equalizers--Their Performance and Application to Time-Variant Multipath Channels

Abstract: This paper presents two types of adaptive lattice decisionfeedback equalizers (DFE), the least squares (LS) lattice DFE and the gradient lattice DFE. Their performance has been investigated on both time-invariant and time-variant channels through computer simulations and compared to other kinds of equalizers. An analysis of the self-noise and tracking characteristics of the LS DFE and the DFE employing the Widrow-Hoff least mean square adaptive algorithm (LMS DFE) are also given. The analysis and simulation results show that the LS lattice DFE has the faster initial convergence rate, while the gradient lattice DFE is computationally more efficient. The main advantages of the lattice DFE's are their numerical stability, their computational efficiency, the flexibility to change their length, and their excellent capabilities for tracking rapidly time-variant channels.

Multidimensional, convolutionally coded communication systems

Abstract: A family of multi-dimensional convolutionally coded modulation systems achieves enlarged minimum distance between possible sequences of signal points, reduced number of error events with the minimum distance, acceptable peak-to-average power ratio, reduced number of signal points in each constituent two-dimensional constellation, immunity to rapid carrier phase changes, and reduced complexity, resulting in a reduced error probability when maximum likelihood decoding is used. These advantages are achieved by the construction and by the partitioning into subsets of the multi-dimensional constellation, by the design of convolutional codes using those multi-dimensional subsets, by using a bit converter and a block encoder to convert a multi-dimensional constellation mapping into multiple two-dimensional constellations mappings, and by a simplified decoding technique.

Coded modulation system using interleaving for decision-feedback equalization

Abstract: In a communication system, the combined advantages of decision feedback equalization and delayed decoding are achieved in a receiver by interleaving the signal points at the transmitter, and deinterleaving them at the receiver so that sufficiently reliable delayed decoder decisions can be used in estimating the distortion component of the received signal presently being processed in the decision feedback circuit.

Comments on "congestion control in TCP/IP internetworks"

Abstract: The article "Congestion control in IP/TCP Internetworks" by John Nagle is an excellent illustration of problems inherent in Arpanet and Milnet technology. The article describes a series of congestion related performance difficulties in a TCP/IP network at Ford Aerospace, and suggested some "cures".What in fact the article describes is what appear to be adequate "band-aids" for the basic inadequacies of Arpanet technology. However, it fails to address the root causes of the performance difficulties that Mr. Nagle discusses. It is suggested that all of these problems result from an uncritical adherence to the Arpanet paradigm, without regard to the research and standardization work of the past 15 years.

Frame synchronization in trellis-coded communication systems

Abstract: Frame synchronization is accomplished in a trellis-coded communication system by causing the sequence of signal points that results when the receiver incorrectly determines the start of each frame to be an impermissible sequence, and detecting the existence of the impermissible sequence by monitoring the rate of occurrence of non-zero difference between the minimum branch metric and the minimum path metric of a maximum likelihood decoding algorithm, such as the Viterbi decoding algorithm. In another aspect, an interleaver and a deinterleaver are used to assure that impermissible sequences result when frame synchronization is lost.

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors

Abstract: Apparatus is described for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them. The apparatus comprises data transfer circuitry con­ nected between the processors for enabling the data to be transferred. A program instruction decoder is associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring. Routing circuitry carries the data transfer com­ mands from the first processor to the program instruction decoder for decoding and executing to provide signals to the data transfer circuitry to effect a transfer of data.

Self-Diagnosis in Distributed Systems

Abstract: This paper deals with computer system diagnosis that is performed by a system itself, rather than by an outside mechanism. The devices performing the diagnosis and the devices communicating diagnostic information are included in the system model and may be potentially faulty. This paper differs from previous work in several ways. A more general diagnostic model is used that permits analysis of a larger class of systems, and the diagnostic goals are more closely matched to realistic self-diagnosis problems. In addition, there are differences in assumptions regarding test invalidation and effects of faults on communication that produce greater self-diagnosibility while accurately modeling faulty system behavior.

CMOS input buffer accepting TTL level inputs

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V A and V B , FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.

New forms of LS lattice algorithms and an analysis of their round-off error characteristics

Abstract: New formulas are presented for direct updating of the reflection coefficients in the a priori and a posteriori forms of the least squares (LS) lattice algorithms. An analysis of the numerical characteristics of the new LS lattice forms is given and a comparison is made with the numerical characteristics of the conventional LS lattice algorithms. Computer simulation results are provided on the numerical accuracy of conventional and new LS lattice algorithms for several values of finite word length.

Backup power system

Abstract: Backup power is provided for primary power supplies that serve several loads by providing fewer backup power supplies than the number of primary power supplies, generating power fault information indicative of the failure status of the primary power supplies, and connecting the backup power supplies each in parallel to one of the failed primary power supplies in response to power fault signals.

An architecture for routing in the ISO connectionless internet

Abstract: The ISO Connectionless Internet Protocol provides a uniform network service over many types of subnetworks. The protocol has currently progressed to the status of draft international standard (DIS 8473). Ideally, the Internet protocol allows for a high degree of connectivity in a global packet-switched network. However, much work needs to be done in the area of routing before this becomes possible in practice.

Data communication network

Abstract: A data communication network (10) over which data handling devices (14) can transmit and receive packets among themselves has a bus (22), a number of subnetworks (12) leach having interfaces for connecting a number of devices to each subnetwork), a concentrator (20) for connecting each interface to the bus, each concentrator having a transceiver (110) for transmitting, to the bus and to devices connected to each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating from other subnetworks (received packets), collision avoidance circuitry for monitoring transmission attempts by devices connected to the subnetwork, for detecting competing transmission attempts that would create a collision on the subnetwork, and, upon such detection, permitting a selected attempt to enter the subnetwork, while preventing other attempts from entering it, collision detection circuitry for monitoring the bus and preventing all attempted transmissions from entering the bus whenever a packet from another subnetwork is present on the bus, circuitry for generating a collision signal upon detecting competing transmission attempts, a network interface unit (NIU) (16) associated with each device to cause withdrawal of an attempted transmission by that device upon receipt of a collision signal, a transmit channel over which transmitted packets are transmitted to the bus, a receive channel over which received packets are transmitted to devices connected to each subnetwork, a station interface unit (SIU) (18) intermediate the NIU and concentrator, a first transmit connector over which transmitted packets pass from the NIU to the SIU, a receive connector over which received packets pass from the SIU to the NIU, a collision signal connector over which collision signals pass from the SIU to the NIU, a second transmit connector over which transmitted packets pass from the SIU to the transmit channel, a combined receive and collision signal connector over which collision signals pass from the concentrator to the SIU, and over which received packets pass from the receive channel to the SIU, and demultiplexing circuitry in the SIU for routing collision signals to the collision signal connector and received packets to the receive connector.