Showing papers by "Codex Corporation published in 1992"

Device and method for implementing queueing disciplines at high sspeeds

Abstract: A device (800) and method (900) are included for providing a high-rate queueing discipline in an information network system having a plurality of traffic classes. The high-rate queueing discipline is based on a scan table-based dequeueing scheme having a scan table that is precomputed and stored in memory, thus facilitating rapid processing of different traffic class information. The device and method are particularly useful in a fast packet system.

Device and method for combining precoding with symbol-rate spectral shaping

Abstract: The device and method provide precoding and symbol-rate transmitter spectral shaping of signals representative of digital information. The invention improves reliability of reception in the presence of non-Gaussian channel noise. The present invention also provides a flexible way of choosing between linear equalization, precoding without spectral shaping, and precoding with spectral shaping.

Circuit and method of switching between redundant clocks for a phase lock loop

Abstract: A phase lock loop monitors the frequency of redundant input clock signals (REFCLK₁AND REFCLK₂) and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal (RC_CLK) maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Corrections to 'The LMS algorithm with delayed coefficient adaptation'

Abstract: The analysis in an earlier paper (see Trans. Acoust. Speech and Signal Processing, vol.37, no.9, p.1397-405, 1989) is improved by correcting an error in the derivation of the system equation. After the correction, the system equation is modified, and thus, so are the related analytical results. >

Rate-based adaptive congestion control system and method for integrated packet networks

Abstract: An adaptive congestion control device (600) and method provides for minimizing congestion on a basis of independent congestion level indicators (626). The invention further provides efficient recovery in an integrated packet network (17, 26, 32, 38) that becomes congested. In addition, the invention ensures that a user may utilize the network on a space-available basis when capacity is available in the network.

Speech coder and method having spectral interpolation and fast codebook search

Abstract: A novel spectral interpolation (500, 600) and efficient excitation codebook search method (700) developed for a Code-Excited Linear Predictive (CELP) speech coder (100) is set forth. The interpolation is performed on an impulse response of the spectral synthesis filter. As the result of using this new set of interpolation parameters, the computations associated with an excitation codebook search in a CELP coder are considerably reduced. Furthermore, a coder utilizing this new interpolation approach provides noticeable improvement in speech quality coded at low bit-rates.

Network management interface with internal DSD

Abstract: Apparatus for interfacing a network manager to a network of communication devices over a single communications channel of a plurality of signals is disclosed. Each communication device of the network is uniquely assigned a poll address for communication selection by the network manager which is operative to establish communication with a communication device of the network by transmitting the poll address thereof over the single communication channel. The network of communication devices are coupleable together in a daisy chain through input and output port circuits thereof to form the single communications channel. The input port circuit of each communications device receives and transmits signals from and to the single communications channel upstream of its position in the daisy chain and the output port circuit of each receives and transmits signals from and to the single communications channel downstream of its position in the daisy chain. In addition, the input port circuit of the communication device in the first position of the daisy chain is coupleable to the network manager for receiving signals, including the poll address, therefrom and for transmitting signals thereto. Each communication device further includes a control circuit which is coupleable to both the input and output port circuits thereof for governing the receiving and transmitting operations of each based on the poll address transmitted over the single communications channel by the network manager.

Associative cam apparatus and method for variable length string matching

Abstract: A variable length string matcher finds the longest string in a stored sequence of data elements (e.g., in a history buffer) that matches a string in a given sequence of data elements. The matcher includes circuitry that operates iteratively to compare data elements of the strings and determine the longest matching string based on when an iteration does not result in issuance of a match signal. In another aspect, the history buffer is an associative content addressable memory (CAM), and the string matcher uses absolute addressing of the CAM to determine the longest matching string.

Sequential acquisition of PN sequences for DS/SS communications: design and performance

Abstract: The performance of sequential acquisition of m sequences, based on the sequential probability ratio test (SPRT), is studied. The authors consider a sliding correlator-type structure for the acquisition scheme, which the mean acquisition time is proportional to the average number of samples used for a synchronization test. Sequential acquisition requires the knowledge of the partial correlation of the pseudonoise (PN) sequence, however, as the partial correlation of an m sequence is difficult to model the authors propose an approximate upper bound. This is then piecewise linearized and used for designing the SPRT which is then compared to the fixed-dwell time technique, a scheme using the fixed sample size test. Numerical results show that the saving of acquisition time by the SPRT increases as the desired probabilities of errors and/or the input SNR decrease. Analytic results are verified by computer simulation. >

Phase lock detection in a phase lock loop

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal when the first and second digital input signals have a first logic state at a first transition of a control signal and a second logic state at a second transition of the control signal. One false lock triggers an out-of-phase status indicator. The lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. The first and second digital input signals may operate with a non-50% duty cycle.

Trellis precoding for modulation systems

Abstract: In general the invention features mapping a digital data sequence into a signal point sequence for data transmission over a channel characterized by a non-ideal response, by selecting the signal point sequence from a subset of all possible signal point sequences based on the digital data sequence and upon the response, all possible signal point sequences in the subset lying in a fundamental region of a filtered trellis code, the fundamental region being other than a simple Cartesian product of finite-dimensional regions.

Device and method for asynchronous cyclic redundancy checking for digital receivers

Abstract: A device and method for asynchronous cyclic redundancy checking (CRC) for digital receivers includes utilizing a finite impulse response (FIR) filter, and comparing and gating circuits. The FIR filter may contain a first multiple delay system unit (102) and a first logic gating system (104). The comparing and gating circuit may contain a second multiple delay system unit (106), and a second logic gating system (110). The device and method is implementable, where desired, utilizing a computer program. The invention provides a faster determination of a CRC frame synchronization on a received digital signal.

Methods for communication-network reliability analysis: probabilistic graph reduction

Abstract: The authors have designed and implemented a graph-reduction algorithm for computing the k-terminal reliability of an arbitrary network with possibly unreliable nodes. The two contributions of the present work are a version of the delta-y transformation for k-terminal reliability and an extension of Satyanarayana and Wood's polygon to chain transformations to handle graphs with imperfect vertices. The exact algorithm is faster than or equal to that of Satyanarayana and Wood and the simple algorithm without delta-y and polygon to chain transformations for every problem considered. The exact algorithm runs in linear time on series-parallel graphs and is faster than the above-stated algorithms for huge problems which run in exponential time. The approximate algorithms reduce the computation time for the network reliability problem by two to three orders of magnitude for large problems, while providing reasonably accurate answers (relative error less than 10/sup -3/) in most cases. >

Vocabulary memory allocation for adaptive data compression of frame-multiplexed traffic

Abstract: A method of and apparatus for allocating memory for storage of vocabularies used in adaptive data compression of a frame-multiplexed data stream of a data communications network. More specifically, a memory (fig. 1, Va; fig.3, 40) of a data compression encoder of the network is partitioned into a plurality of sections for the temporary storage of a corresponding plurality of data compression vocabularies. A memory section of the plurality is assigned to a current frame of the frame-multiplexed data stream based on information of the current frame for storage of a vocabulary created adaptively from the current frame.

Phase lock loop charge pump with symmetrical charge and discharge currents

Abstract: A charge pump in a phase lock loop equalizes the charge and discharge currents flowing into the filter capacitor independent of the loop node voltage for providing a linear VCO output frequency. The potential at the output of the charge pump determines whether the charging/discharging current is decreased or increased. An active up control signal to increase VCO output frequency and a low level potential at the output of the charge pump limits the charging current to the loop filter while increasing the discharge current. An active down control signal to decrease the VCO output frequency and a high potential at the output of the charge pump limits the discharging current while increasing the charge current. The voltage change at the output of the charge pump in response to the up control signal is made equal to the voltage change during the down control signal for providing equal charge and discharge currents to the loop filter independent of the loop voltage.

Power on reset circuit having hysteresis inverters

Abstract: A power on reset circuit uses a first inverter with hysteresis operating in response to a first power supply potential to develop a first reset signal when the first power supply potential is greater than a first predetermined threshold. A second inverter with hysteresis also operates in response to the first power supply potential for developing a second reset signal when the first power supply potential is greater than a second predetermined threshold. The first reset signal disables the second inverter until the first power supply potential reaches the first predetermined threshold. A delay circuit delays the second reset signal to ensure the first power supply potential is fully operational before indicating a ready condition.

Integrating life-cycle cost and cost-of-ownership in the commercial sector

Abstract: The author describes two models, the LCC (life cycle cost) model and the COO (cost of ownership) model, and their use as an aid in meeting the objective of creating products that have the lowest LCC for both the manufacturer and the customer. First, the what and why of the LCC analysis process are discussed, and the objectives are defined. The model is described in terms of the major cost elements, as well as the various model variables. The use of the results as a planning tool in the decision-making process is emphasized. Sample baseline runs are provided to demonstrate the implementation and utility of the model, and illustrate the reporting formats. Then, the COO model is presented to provide the customer perspective of LCC. The utility of the model in helping to leverage product sales and services is explained. An overview of the COO model is also furnished in terms of mechanization, input data, and application. Sample runs and tradeoffs are made to illustrate the relative COO for varying levels of service maintenance contract options. >

Novel device and method for precoding___________________________

Abstract: A novel precoding technique (900) and device (100) allows transmission of a stream of signal points over a channel h(D) to provide efficient data transfer in the presence of intersymbol interference and noise at data rates approaching channel capacity. This new technique may be combined with trellis-coded modulation and works with any signal constellation. In addition, the present invention allows decoupling signal constellation shaping, a significant improvement over prior precoding techniques. Thus, the present invention simplifies shaping and allows signaling at fractional rates without constellation switching.

Novel device and method for precoding

Abstract: New device (100) and technique (900) for precoding a transmit signal point stream on a channel h (D) to ensure the efficient transfer of data in the presence of intersymbol interference and noise under conditions of flow rates data near the channel flow capacity. This new technique can be combined with the modulation coded by lattice works and with any constellation signals. In addition, this invention allows to decouple signal constellation shaping and therefore represents a significant improvement over the prior art precoding techniques. This invention simplifies the layout and allows to transmit signals to the fractional flow rates without switching the constellation.