Showing papers by "Teradyne published in 1989"

IC quality and test transparency

Abstract: It is shown that extremely high single-stuck fault coverage is necessary for high-quality products. Even 100% single-stuck fault coverage may not guarantee adequate quality. Results are presented that extend previous work and show that for high required IC quality, process yield has a negligible effect on required test thoroughness. The extensions consist of: removing the assumption of a one-to-one correspondence between chip defects and single-stuck faults; demonstrating that for high quality levels the dependence of quality on test coverage is linear rather than exponential and that for high yields, the dependence of quality on yield is also linear; and showing that the yield used in the calculations should be functional rather than die yield. The theoretical results are compared with data obtained from measurements at a production IC facility. >

Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels

Abstract: The test of embedded clusters of conventional logic via boundary scan virtual channels has been shown to be a practical way to test and diagnose structural faults where these clusters are inaccessible to standard ATE (automatic test equipment) channels. Huge quantities of data can be created by this technique, which could result in prohibitive storage requirements and poor throughput. By use of topological data compression and special hardware, the storage requirement can be small and test times limited only by the speed of the boundary scan path. After discussing test pattern generation, the boundary scan environment, and the serialization of test patterns and algorithmic patterns, the author presents applications examples. >

Printed circuit boards with improved electrical current control

Abstract: Printed circuit board with internal laterally extending electrically conductive element and perpendicularly thereto extending conductive element larger at a pin-receiving level than at the laterally extending conductive element level.

An integrated analog test simulation environment

Abstract: An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap. >

Interfacing, often a performance bottleneck between ATE and device under test

Abstract: Problems in adapting the interface of VLSI test systems to the device under test (DUT) are reviewed. The focus is on efforts to avoid the electrical degradation of the DUT, especially with increasing operating speeds and increasing pincounts. The channel cards or pin electronics of the automatic test equipment (ATE) have to be flexible and as close to the DUT as possible, and the electromechanical interface, known as the device interface board (DIB) or loadboard, has to be of high quality. For an ATE of given and known performance, the final results therefore very often depend on the performance of such DIBs. Variations of test results caused by wiring on the DIB may decrease the total yield or let the device get binned into a lower category. In the production test areas, there is an inherent tendency to save costs and hence use a so-called 'mother-daughter' board concept for DIBs. For slower NMOS devices and generally for devices with uncritical timing, this concept is acceptable. However, for modern CMOS devices with fast switching outputs, the insertion of pogo pins in the transmission line and the availability of fewer pins for the ground connections could severely degrade the performance of testing. >

A testing methodology for new-generation specialty memory devices

Abstract: The authors describe the new requirements placed on tester hardware and software by new-generation specialty memory devices. Examples of real devices, including video RAMs, FIFOs, cache tags and SSRAMs (synchronous static RAMs), are used to illustrate the points. It is noted that specialty memories are creating complexities which demand new approaches in both hardware and software. Multiport devices, such as the TMS44C251 video RAM, are more easily tested on synchronized dual pattern generator test systems because the device program development process is eased and true independence of expect and drive data can be obtained. A method, implemented in hardware, by which data outputs can be delayed a few cycles from the presentation of address is required to test devices such as the MCM6294 SSRAM which contains latches on its inputs and outputs. IDT's 72103 FIFO, with its complicated timing requirements and multiple setup modes, calls for an increased number of clocks and for timing, data, and formatting capabilities to be switchable at pattern speeds. Software tools also need enhancements to manage the complexities of specialty devices. >

Calculating the effective pattern rate for high-speed board test applications

Abstract: A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board under test. >

Testing and characterization of ASICs by the user

Abstract: The use of simulation data obtained during user development of an application-specific IC (ASIC) to generate a test program is discussed. It is shown that the quality of the test program generated in this way depends on the accuracy of the simulation and the thoroughness of the applied stimuli. The simulation needs to take account of both the tester and the device specifications. The tester imposes certain restraints such as minimum pulse width and restrictions on the relative placing of edges. If the simulator is not truly dynamic, there can be problems with the resulting test program in two key areas. The setup and hold times of the inputs may not be correctly verified, and position of the output may be wrongly predicted. A tester-per-pin architecture has several advantages over a shared-resource tester. These advantages mean saving or shortening of certain steps in the conversion process, easy characterization, and faster response for changes. >