Showing papers in "IEEE Transactions on Industrial Electronics in 1989"
TL;DR: In this article, an identity state observer for the permanent magnet synchronous motor is derived which reconstructs the electrical and mechanical states of the motor from current and voltage measurements, and the observer operates in the rotor frame and estimates direct and quadrature stator currents, rotor velocity, and rotor position.
Abstract: An identity state observer for the permanent-magnet synchronous motor is derived which reconstructs the electrical and mechanical states of the motor from current and voltage measurements. The observer operates in the rotor frame and estimates direct and quadrature stator currents, rotor velocity, and rotor position. Since the rotor position is estimated, the rotor reference frame is approximated using the latest rotor position estimate. The motor dynamics and the transformation into the estimated rotor frame are nonlinear, and thus the observer and observer error dynamics are nonlinear. Therefore, stability is analyzed using a linearized error model. Simulations including realistic measurement disturbances are used to investigate the global stability and accuracy of the observer. >
246 citations
TL;DR: In this paper, the robust controller has very simple structures and can be divided into two separate parts: a servo controller and an auxiliary controller, which cancels out the plant uncertainties directly without the use of the high loop gain principle.
Abstract: The robust controller has very simple structures and can be divided into two separate parts: a servo controller and an auxiliary controller. The two controllers are designed independently. The function of the auxiliary controller is to cancel out the plant uncertainties directly without the use of the high loop gain principle. Interpretation of robot controller as a signal-synthesis adaptive controller is given. Practical implementation issues of the auxiliary controller are discussed. Simulations of a design example with large parameter uncertainty, nonlinearity, and external disturbance are presented to demonstrate the effectiveness of the design technique. This technique is further tested with success in an experimental study of joint position control of a PUMA 560 robot arm. >
181 citations
TL;DR: In this article, a new type of high-frequency high-efficiency resonant DC/DC converter is proposed, analyzed, and verified experimentally, which is called a class-E converter because it consists of an E inverter and a E rectifier, and it operates safely with a short circuit at the output.
Abstract: A new type of high-frequency high-efficiency resonant DC/DC converter is proposed, analyzed, and verified experimentally. It is called a class-E converter because it consists of a class-E inverter and a class-E rectifier. The class-E rectifier acts as an impedance inverter and is compatible with the class-E inverter. Consequently, the converter can operate with load resistances from a full load to infinity while maintaining zero-voltage switching of the transistor in the inverter and the diode in the rectifier. It operates safely with a short circuit at the output. Because of a high value of the load quality factor Q/sub 1/, a narrow frequency range suffices to regulate the DC output voltage over the whole load range. The measured relative bandwidth was delta f/f/sub min/=42.2% as the load resistance was varied from 70 Omega to open circuit. The measured efficiency at the full load was 89% with a 9 W output power at 1 MHz. A family of class-E/sup 2/ resonant DC/DC power converters is given. The possibility of reduction of class-E/sup 2/ converters to lower-order resonant and pulse-width-modulation converters is shown. >
164 citations
TL;DR: I/sub DDQ/ monitoring is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage as mentioned in this paper.
Abstract: Quiescent power supply current (I/sub DDQ/) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, I/sub DDQ/ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer test vectors than a stuck-at test set. Individual CMOS ICs from three different fabrication sites had a unique pattern or fingerprint of elevated I/sub DDQ/ states for a given test set. When I/sub DDQ/ testing was added to conventional functional test sets, the percentage increase in failures ranged from 60% to 182% for a sample of microprocessor, RAM, and ROM CMOS ICs. >
155 citations
TL;DR: In this article, a steady-state analysis and experimental results for a dual sepic pulsewidth-modulated (PWM) DC/DC power converter for both continuous and discontinuous modes of operation are presented.
Abstract: A steady-state analysis and experimental results for a dual sepic pulse-width-modulated (PWM) DC/DC power converter for both continuous and discontinuous modes of operation are presented. The converter is dual to a sepic converter, but it can also be derived from a forward converter by replacing one of its rectifier diodes with a coupling capacitor. The circuit acts as a step-down or step-up converter, depending on the value of the ON switch duty cycle. The transformerless version of the converter has a positive DC/DC voltage transfer function. Therefore, the circuit is suitable for distributed power systems. Design equations for all circuit components are derived. Experimental results measured at 100 kHz were in good agreement with theoretical predictions. >
106 citations
TL;DR: In this article, a practical method for calculating the harmonic currents of a three-phase bridge rectifier with a DC filter, taking into account the AC source reactance, is proposed.
Abstract: A practical method is proposed for calculating the harmonic currents of a three-phase bridge uncontrolled rectifier with a DC filter, taking into account the AC source reactance. The method is based on the frequency-domain method and the rectifier switching functions. Analytical equations for the harmonic currents on both the DC and AC sides are derived. The validity of the method is demonstrated by comparison with the results of time simulation. The approach can be extended to the harmonic analysis of a thyristor rectifier as well as a rectifier with unbalanced line conditions. >
106 citations
TL;DR: In this paper, a static three-phase to threephase power converter for an AC drive with a unity power factor and reduced harmonics on the line side is presented, where the method of predictive optimization is used for the control of the power converter.
Abstract: A novel concept for a static three-phase to three-phase power converter for an AC drive with a unity power factor and reduced harmonics on the line side is presented. The power circuit comprises two back-to-back connected six-pulse bridges having no energy storage elements in the DC link. This permits pulse-width modulation (PWM) control in both bridges while requiring active turn-off semiconductor switches in only one bridge. The line-side harmonics are suppressed by a three-phase second-order filter. The method of predictive optimization is used for the control of the power converter. The complex control structure of the system is based on an online prediction of space vector trajectories. The steady-state operation of the system is exemplified by simulation results. >
100 citations
TL;DR: In this article, it is shown that extremely high single-stuck fault coverage is necessary for high quality products and that the dependence of quality on test coverage is linear rather than exponential.
Abstract: It is shown that extremely high single-stuck fault coverage is necessary for high-quality products. Even 100% single-stuck fault coverage may not guarantee adequate quality. Results are presented that extend previous work and show that for high required IC quality, process yield has a negligible effect on required test thoroughness. The extensions consist of: removing the assumption of a one-to-one correspondence between chip defects and single-stuck faults; demonstrating that for high quality levels the dependence of quality on test coverage is linear rather than exponential and that for high yields, the dependence of quality on yield is also linear; and showing that the yield used in the calculations should be functional rather than die yield. The theoretical results are compared with data obtained from measurements at a production IC facility. >
87 citations
TL;DR: In this article, three alternative approaches for eliminating steering discontinuities are presented: changing the steering mechanism, changing the guide-point on the cart, or changing the curves on the path.
Abstract: Three alternative approaches for eliminating steering discontinuities are presented: changing the steering mechanism, changing the guide-point on the cart, or changing the curves on the path. The first approach requires a steering mechanism that allows the cart to move in any direction without changing its heading. The most common configurations in an automatically guided vehicle are the steered-wheel and differential-drive types. The second approach may be a reasonable choice for differential-drive carts but less so for steered-wheel carts because of their limited maneuverability. For applications where the third approach is preferred, two types of curves providing continuous steering functions for both steered-wheel and differential-drive carts are proposed: Cartesian quintics for lane changes and polar splines for symmetric turns of arbitrary angle. These curves have computationally simple, closed-form expressions that provide continuous curvature and precise matching of the boundary conditions at the line-curve junctions on the paths. >
80 citations
TL;DR: In this paper, the authors present a tutorial review of power electronics and drives in which the status of the technology and its future are discussed, focusing on power semiconductor devices, converter circuits, AC machine control and microcomputer applications in power electronics systems.
Abstract: The author presents a tutorial review of power electronics and drives in which the status of the technology and its future are discussed. He focuses on power semiconductor devices, converter circuits, AC machine control, and microcomputer applications in power electronics systems. He examines the impact of computer-aided design and artificial intelligence, and he summarizes the technological trends. He predicts that the technology will grow with increasing momentum as component technologies continue to grow. >
73 citations
TL;DR: The authors focus on the implementation of a variable structure systems (VSS) controller with smoothing laws in the design of effective tracking control for multi-input, multi-output robotic arms.
Abstract: The authors focus on the implementation of a variable structure systems (VSS) controller with smoothing laws in the design of effective tracking control for multi-input, multi-output robotic arms. The controller is realized by selecting powerful smoothing methods, such as balance conditions or their simplification, to reduce or remove undesirable chattering while keeping the robust characteristic that rejects system uncertainties. Giving careful consideration to actual system constraints, a design principle for selecting different smoothing methods is obtained and confirmed by experimental results. >
TL;DR: A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits and the methods presented are used to increase the controllability and observability of the circuit design.
Abstract: A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered. >
TL;DR: In this paper, a technique to develop a simple, nonlinear dynamic model (from measurements of flux linkage) which captures all of the relevant dynamics of the motor over its entire operating regime is described.
Abstract: A technique to develop a simple, nonlinear dynamic model (from measurements of flux linkage) which captures all of the relevant dynamics of the motor over its entire operating regime is described. A least squares data reduction algorithm that handles the analyses in a natural way to generate bivariate polynomials to approximate the flux linkage is given. Comparisons with a theoretical method and other measurements are presented. >
TL;DR: In this paper, the authors present an approach to the steady-state analysis of the switch-reluctance motor (SRM) drive including the effects of stator winding resistance, input filter parameters, and snubber circuits.
Abstract: The principle of operation of the switched-reluctance motor (SRM) drive demands that the motor and converter be treated as one unit Little has been done to develop a complete analysis of this motor-converter combination The authors present an approach to the steady-state analysis of the drive including the effects of stator winding resistance, input filter parameters, and snubber circuits, which are often neglected The analysis yields current, voltage, torque, and back-EMF (electromotive force) waveforms that provide guidelines to the optimal design of the drive Experimental verification is provided for a 6/4 pole prototype SRM drive, and it is shown to be in good agreement with the simulation results It is noted that this approach can be applied to any other motor-converter combination with minimal modification >
TL;DR: The performance of the IEEE 802.4 priority mechanism in handling distributed real-time control traffic is examined and a timer assignment technique is presented to satisfy the worst-case access delay requirements of real- time control applications.
Abstract: The performance of the IEEE 802.4 priority mechanism in handling distributed real-time control traffic is examined. A timer assignment technique is presented for such applications. The timers are set to satisfy the worst-case access delay requirements of real-time control applications. Other applications that are not time constrained can be supported simultaneously. Under certain conditions, such applications can also be guaranteed a minimum bandwidth allocation. Simulation results are used to evaluate the timer assignment scheme. >
TL;DR: In this paper, a zero-voltage switching technique is achieved for both class-E inverters and rectifiers, and the efficiency of the converters is very high at switching frequencies in the megahertz range.
Abstract: Analysis and design rules are presented for three class-E switching-mode DC/DC power converters, each with a capacitive impedance inverter. Experimental results are given for one of the converters. A zero-voltage switching technique is achieved for both class-E inverters and rectifiers. Therefore, the efficiency of the converters is very high at switching frequencies in the megahertz range. By applying a capacitive impedance inverter, lossless operation of the class-E inverter can be obtained for a wide range of converter load resistance, from full load to infinity. Experimental results are in excellent agreement with the theoretical calculations. Only a 12% relative bandwidth of the switching frequency is required to maintain a constant DC output voltage for the load resistance from full load to infinity at about 1 MHz with 15-W output. >
TL;DR: The design of a versatile module test and maintenance controller (MMC) that can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components is presented.
Abstract: The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute, the number of test buses they control, and the expansion units they use. A simple yet novel circuit, called a test channel, is used in an MMC. The MMC processor can control a test channel by reading/writing its internal registers. Once initialized by the MMC processor, a test channel can carry out most of the testing of a chip. Thus the processor need not deal with detailed test-bus control sequences since they are generated by the test channel. This strategy greatly simplifies the development of test programs. The proposed MMC can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components. Some of its self-test features are presented. >
TL;DR: In this paper, an offline uninterruptible power supply (UPS) or emergency power system with zero transfer time is presented, where the battery charging circuit is integrated into the transformer and improves the dynamic output response during line-mode operation.
Abstract: An offline uninterruptible power supply (UPS) or emergency power system with zero transfer time is presented. The principal application is to personal computers and systems. The power transformer, a triport-like transformer, acts as an inverter and as a voltage stabilizer with no external loading coil. It is made with commercial EI scrapless laminations. The battery charging circuit is integrated into the transformer and improves the dynamic output response during line-mode operation. The result is robust, short-circuit-proof equipment with harmonic distortion of lower than 3%, a static output stability better than 1.5%, and a very high reliability. >
IBM1
TL;DR: The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans.
Abstract: The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans. >
TL;DR: The authors discuss the need for basic design for testability methods that must be used to alleviate the problems of circuit complexity, IC defect anomalies, and economic considerations that prevent complete validation of VLSI circuits.
Abstract: Defect-free integrated circuits (IC) cannot be guaranteed by VLSI circuit manufacturers. Circuit complexity, IC defect anomalies, and economic considerations prevent complete validation of VLSI circuits. These VLSI test problems are especially acute in high-reliability designs and will only worsen as IC circuit size increases. Designers of IC, board, and system projects must be aware of the difficult engineering challenges that are involved in verifying high-quality ICs. The authors discuss these topics and emphasize the need for basic design for testability methods that must be used to alleviate these problems. >
TL;DR: The accuracy and speed of the improved fault diagnosis algorithms using a signed directed graph as a model of the system are examined by its application to data obtained in fault diagnosis experiments on tank-pipeline systems.
Abstract: The fault diagnosis algorithms using a signed directed graph (SDG) as a model of the system is useful in the real-time diagnosis of failures that occur in chemical processes. The accuracy of the algorithm has been improved so that it can select the candidates that are most likely to be the real origin of failure, utilizing the time when the measured variables begins to show abnormality as the representation of the dynamic characteristic of the measured variable. The accuracy and speed of the improved algorithm have been examined by its application to data obtained in fault diagnosis experiments on tank-pipeline systems. >
TL;DR: The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing.
Abstract: The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the problems associated with testing basic circuit configurations for different types of commonly used analog macros. Using the recommended architecture to gain access to control and observation test points in the analog portions of the mixed analog/digital ASIC, a series of analog test tables for several different analog functions have been derived. The analog test procedures are independent of any digital design for testability that might be used in the digital portions of the ASIC. General testing procedures for current analog/digital ASICs are described along with desirable characteristics for testers for this type of circuit. >
TL;DR: In this paper, a high-order high-frequency LCC-type capacitive coupled parallel resonant converter (LCC-LCC) operated in the continuous-conduction mode is presented.
Abstract: A novel approach to the analysis of design of a high-order high-frequency LCC-type capacitive coupled parallel resonant converter (PRC-LCC) operated in the continuous-conduction mode is presented. The presence of an additional capacitor in series with the inductance of the conventional PRC results in a converter with more desirable control characteristics. It is shown that, at switching frequencies lower than the resonant frequency, the gain of the LCC-type converter is lower than the grain of the conventional PRC. This facilitates the converter design with a lower turn-ratio transformer and therefore allows for a higher operating frequency. The complete state-plane diagram of the LCC-type converter, from which a set of steady-state characteristic curves is plotted, is given. Various design curves for component value selections and device ratings are given. A design example with computer simulation results is presented. >
TL;DR: In this article, the design of a battery-supplied fluorescent lamp for automotive, emergency, or portable light sources has been presented, where each fluorescent tube has its own driver circuit that exhibits high efficiency (over 80%), simple design and low cost.
Abstract: The author presents the design of a battery-supplied fluorescent lamp for automotive, emergency, or portable light sources. Each fluorescent tube has its own driver circuit that exhibits high efficiency (over 80%), simple design, and low cost. The driver circuit operates at a high frequency (50 kHz) and has an electronic ballast control, symmetrical tube driving, and semiresonance ignition. These operating conditions are optimal, and they provide a long tube life and high illumination. >
TL;DR: The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation and present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques.
Abstract: The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability. >
TL;DR: In this article, an optimal digital redesign technique for finding a dynamic digital control law from the given continuous-time counterpart by minimizing a local quadratic performance index is presented. But this method requires a large sampling period.
Abstract: The authors present a novel optimal digital redesign technique for finding a dynamic digital control law from the given continuous-time counterpart by minimizing a local quadratic performance index. The quadratic performance index is chosen as the integral of the weighted squared difference between the states of the original closed-loop system and those of the digitally controlled open-loop system at any instant between each sampling period. The developed optimal digital redesign control law enables the states of the digitally controlled open-loop system to match closely those of the original closed-loop system at any instant between each sampling period, and it can easily be implemented using microcomputers with a relatively large sampling period. An illustrative example is presented to demonstrated the effectiveness of the proposed method. >
TL;DR: In this article, a single-chip microcomputer control of a pulsewidth-modulated (PWM) inverter for motor drive applications is presented, where the PWM pattern generation and the system control of the inverter are achieved by software of the 8-bit single-Chip microcomputer.
Abstract: Single-chip microcomputer control of a pulsewidth-modulated (PWM) inverter for motor drive applications is presented. The PWM pattern generation and the system control of the inverter are achieved by software of the 8-bit single-chip microcomputer. The single-chip microcomputer has a low processing speed and small memory capacity, disadvantages that can be overcome by the magnetic flux control PWM method. The PWM pattern is generated every 90 mu s. The memory capacity of the PWM look-up table is less than 2 kbytes. Experimental results show that the motor performances are the same as that of the multichip triangular-sinewave PWM inverter. >
TL;DR: In this paper, an ultrasonic-based seam tracking robotic system that guides a nonwelding torch along different welding grooves is presented, where a 100 kHz airborne transducer is used to inspect the workpiece ahead of a welding torch and measure the joint orientation and lateral deviation caused by curvature or discontinuities in the joint part.
Abstract: The description of an ultrasonic-based seam-tracking robotic system that guides a nonwelding torch along different welding grooves is presented. A 100 kHz airborne transducer is used to inspect the workpiece ahead of a welding torch and measures the joint orientation and lateral deviation caused by curvature or discontinuities in the joint part. Data pertaining to the joint orientation and lateral deviation (echo pulse amplitude and time of flight) are obtained periodically by sampling equi-spaced points along the joint as the torch advances. A trajectory-generating algorithm uses this data to calculate the x, y, theta coordinates of the torch-tip trajectory needed to meet the tracking requirements. The experimental results from a feasibility study conducted to determine if this system could be used for tracking during live welding are also presented. >
TL;DR: A tri-module redundant (TMR) multiprocessor system for increased availability to a real-time application is presented and has been used to drive a mobile trolley.
Abstract: A tri-module redundant (TMR) multiprocessor system for increased availability to a real-time application is presented. The system incorporates three homogeneous Z-80 based microcomputers, each with necessary analog/digital I/O facilities and global communication hardware. The software design is modular in nature and is, therefore, cost effective and adaptable for expansion to the N-module redundant (NMR) system. The retry mechanism has been employed for recovery from transient faults. The number of retries is programmable, which makes the system adaptable to an application environment. The system has been used to drive a mobile trolley. >
TL;DR: A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits.
Abstract: A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testability analysis as a guide to design and test generation is discussed. Algorithms for automatic test-pattern generation are summarized. >