Showing papers by "Teradyne published in 2000"

High-speed failure capture apparatus and method for automatic test equipment

Abstract: A failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT) is disclosed. The failure capture circuit includes failure detection circuitry comprising a plurality of channels and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals therefrom into failure information. A failure memory circuit and a high speed link are provided to minimize test time. The high-speed link couples the failure memory circuit to the failure detection circuitry to provide serial data transfer capability therebetween.

Modular electrical connector and connector system

Abstract: A modular connector system for interconnecting printed circuit boards includes a first connector having an insulative housing supporting an array of blade-shaped contacts and a second connector having a complementary array of beam-shaped contacts. Preferably, each beam-shaped contact includes substantially independent coplanar beams which, in use, contact a common surface of a respective blade-shaped contact to provide multiple points of contact. The second connector includes a plurality of modules stacked in parallel. Each module includes a shield plate having an insulative receptacle attached at one end and a row of signal conductors, each having a beam-shaped contact at one end. Each insulative receptacle has a first side in which cavities are provided to receive the beam-shaped contacts of the signal conductor. Each insulative receptacle further includes a second, opposite side in which holes are formed in substantial alignment with the cavities for receiving the blade-shaped contacts of the first connector.

Method of providing software testing services

Abstract: A system that provides easy testing of software objects and reduces the burden on a program developer for maintaining a test system is presented. The system accepts as an input objects and automatically creates test drivers for these objects. The test objects are provided to a test bed comprising an application server where the objects are tested by application of the test drivers. In a preferred embodiment, the test bed comprises a collection of application servers. An application service provider provides the system test driver and the test bed. Access to the test system is provided by passing a representing of the object under test to the application service provided through a network interface. The application service provider provides test services on a fee for service basis.

Low jitter phase-locked loop with duty-cycle control

Abstract: A timing circuit (700) for ATE generates an output clock (710a) from an input clock and controls output pulse width. The timing circuit includes a differential driver (710) having an input that receives the input clock, and having inverting and non-inverting outputs. The inverting output is coupled to a first phase-locked loop (712), and the non-inverting output is coupled to a second phase-locked loop (714). The first and second phase-locked loops respectively generate first and second clocks in response to respective rising and falling edges of the input clock. A combiner circuit (716) converts the first and second clocks into narrow pulse trains, and the pulse trains respectively operate SET and RESET inputs of a SET/RESET flip-flop. The SET/RESET flip-flop generates an output clock having rising edges responsive to rising edges of the input clock, and falling edges responsive to falling edges of the input clock. The timing circuit also includes a frequency divider (924) in feedback path of the phase-locked loops, for establishing a frequency gain of the timing circuit. Pulse width of the output clock is based upon pulse width of the input clock and frequency gain of the timing circuit. To promote timing accuracy, the frequency responses of the phase-locked loops are tailored to selectively filter jitter from the input clock that is uncorrelated with jitter in the ATE, but to pass correlated jitter unattenuated.

Self retained pressure connection

Abstract: A self retained pressure connector is provided that includes a spring action contact surface at a first end and a compliant interference fit contact surface at a second end. The compliant interference fit contact is supported within a conductive hole in a printed circuit board and the spring action surface contact provides an electrical connection to a conductive element disposed on a second surface. The conductive element may, in alternate embodiments, be a surface pad on the second surface or a second self retained pressure connector rotated ninety degrees from the first self retained pressure connector. A differential self retained pressure connection is also described in which a dielectric material is used to electrically isolate a first half of the connector from a second half of the connector.

Techniques for preventing tonal behavior of data weighted averaging algorithm in /spl Sigma/-/spl Delta/ modulators

Abstract: Two techniques for prevention of in-band tones in DWA mismatch noise shaping algorithm are presented. "offset technique" moves in-band tones away from baseband, improving SNR by /spl sim/10 dB, and attenuates maximum in-band tone by as much as /spl sim/25 dB. "Randomized DWA" is a combination of simultaneous randomization and DWA, which attenuates tonal behavior in all frequencies, preventing aliasing of tones or tone shifting for any arbitrary input signal.

Determining the physical structure of subscriber lines

Abstract: A method determines a structure of a subscriber line. The method includes searching a reference set for a match between the subscriber line and a model line of the reference set and identifying that the subscriber line has a specific physical structure. The match is based on electrical properties of the lines. The act of identifying is responsive to finding a match with one of the model lines that has the specific physical structure.

Semiconductor parallel tester

Abstract: A semiconductor parallel tester is disclosed for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.

Automatic test equipment methods and apparatus for interfacing with an external device

Abstract: The invention is directed to techniques for accessing an external device, e.g., a device under test (DUT), from an automatic test equipment (ATE) interfacing apparatus, e.g., a specialized tester or channel card device. In one arrangement, the ATE interfacing apparatus includes a test bus interface for connecting to a test bus of an automatic test system; an external device interface for connecting to an external device; and a translator, interconnected between the test bus interface and the external device interface. The translator receives a memory access instruction from the test bus through the test bus interface. The memory access instruction includes a command and a test bus address. The translator translates the test bus address into an identifier which identifies a portion of the external device, and accesses the identified portion of the external device through the external device interface based on the command and the identifier. Translation of the test bus address into the identifier, and accessing the external device based on the command of the instruction and the identifier alleviate the need for the ATE interfacing apparatus to receive lower level instructions and data from an ATE controller. Accordingly, less time is needed to configure the ATE interfacing apparatus through the test bus resulting in greater overall programming and/or test times and enhanced throughput.

Calibrating single ended channels for differential performance

Abstract: An apparatus and method for deskewing single-ended signals from different driver circuits of an automatic test system provides enough of a reduction in skew to allow differential signals to cross at or near their 50%-points. In accordance with this technique, first and second driver circuits are respectively coupled to first and second inputs of a measurement circuit through pathways having known and preferably equal propagation delays. The first and second driver circuits each generate an edge that propagates toward the DUT, and reflects back when it reaches a respective unmatched load at the location of the DUT. In response to the edge and its reflection, the first and second inputs of the measurement circuit each see a first voltage step and a second voltage step. The interval between the first and second voltage steps is then measured for each input of the measurement circuit. Variable delay circuits disposed in series with the driver circuits are adjusted in response to the measured intervals, to ensure that signals from the first and second driver circuits arrive at the DUT at substantially the same time. The measurement circuit may also measure the slew rates of the signals from the first and second driver circuits. Slew rate adjustment circuits provided with the driver circuits are then adjusted to substantially equalize slew rates from the first and second driver circuits.

Low cost timing system for highly accurate multi-modal semiconductor testing

Abstract: A timing system is disclosed that responds to pattern generation circuitry or producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.

Pattern generator for a packet-based memory tester

Abstract: A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

Circuit and method for improved test and calibration in automated test equipment

Abstract: A preferred embodiment of the present invention provides a time varying signal channel having a series-connected solid state switch interposed between a time varying signal circuit end and a device under test end of the time varying signal channel A DC test channel is connected to the time varying signal channel between the series-connected solid state switch and the device under test end, and has at least one solid state switch interposed along the DC test channel to provide switchable coupling between a DC parametrics circuit side of the DC test channel and the time varying signal channel A time varying signal level calibration channel is connected to the time varying signal channel between the series-connected solid state switch and the time varying signal circuit end, and has at least one solid state switch interposed along the signal level calibration to provide switchable coupling between a DC parametrics circuit side of the signal level calibration channel and the time varying signal channel The time varying signal channel may have a low resistance type solid state switch, while the DC test channel, the signal level calibration channel, or both, may have low capacitance type solid state switches Thus, opto-coupled MOSFETS, pin diodes, or other kind of solid state switches, may be utilized The DC test channel, or the signal level calibration channel, or both, may have a force branch and a sense branch each having a solid state switch

Detector with common mode comparator for automatic test equipment

Abstract: A detector circuit for automatic test equipment samples and tests differential signals. The detector circuit includes a pair of impedances connected in series between first and second legs of a differential input signal. A signal is formed at the junction of the two impedances that equals the common mode voltage of the differential signal. The common mode signal is coupled to the input of a window comparator, which compares the common mode signal with predetermined thresholds. The window comparator generates an output indicative of whether the common mode signal is above, within, or below the predetermined thresholds. Using this approach, the detector circuit can detect errors in differential signals caused by mismatched amplitudes or by timing skew between the first and second input signals. According to one feature, the detector circuit also includes a differential mode detector that receives the first and second input signals. The detector circuit according to the invention thus separately extracts the common mode and differential components of a differential input signal for separate evaluation.

Compensation system and related techniques for use in a printed circuit board inspection system

Abstract: A system and method for compensating pixel values in an inspection machine for inspecting printed circuit boards includes an image acquisition system for providing pixel values from a digitized image to a compensation circuit. The compensation circuit applies one or more compensation values to the digitized pixel values to provide compensated digitized pixel values for storage in a memory. The compensated digitized pixel values are then available for use by an image processor which implements inspection techniques during a printed circuit board manufacturing process. With this technique, the system corrects the errors on a pixel by pixel basis as the pixel values representing an image of a printed circuit board are transferred from the image acquisition system to the memory.

Apparatus for forming a connection between a circuit board and a connector, having a signal launch

Abstract: A circuit board includes (i) a section of circuit board material having a signal conductor, a ground conductor, and dielectric material that separates the signal conductor and the ground conductor, and (ii) a signal launch. The signal launch includes a signal via that contacts the signal conductor and the dielectric material of the section of circuit board material, a first set of ground vias and a second set of ground vias. The ground vias contact the ground conductor and the dielectric material of the section of circuit board material. The first set of ground vias is disposed a first radial distance from the signal via. The second set of ground vias is disposed a second radial distance from the signal via. A coaxial connector mounts to the signal launch of the circuit board in order to provide electrical access to the signal and ground conductors.

Methods and apparatus for forming a fiber optic connection

Abstract: The invention is directed to techniques for forming a fiber optic connection between a first connection assembly that provides alignment members and a second connection assembly that provides grooves such that a central axis of each groove of the second connection assembly is substantially perpendicular with a central axis of a corresponding alignment member of the first connection assembly. Each alignment member/groove pair can be positioned and oriented to control positioning of the first and second connection assemblies relative to each other in a single direction but allow movement in other directions to prevent physical stressing of the connection assemblies. That is, the alignment members of the first connection assembly can be arranged around a periphery of a first array of fiber ends of a first fiber optic cable, and the grooves of the second connection assembly can be arranged around a periphery of a second array of fiber ends of a second fiber optic cable such that the aggregate contribution of each alignment member/groove pair forms a self-aligning mechanism that properly aligns the first and second arrays of fiber ends to provide effective light transfer between fiber optic cables.

Qualifying telephone lines for data transmission

Abstract: The method assesses the suitability of customer telephone lines (12, 13, 14) for data transmission. The method includes selecting a telephone line having tip and ring wires by means of a computer (30) and switch (15), and electrically connecting the tip and ring wires together at a test access (29) adjacent one end of the selected line to produce a common mode configuration. Single-ended electrical measurements are performed on the wires in the common mode configuration by a measurement unit (27) connected to the test access (29) to determine an electrical property of the wires from the measurements.

Failure capture apparatus and method for automatic test equipment

Abstract: A failure capture circuit for identifying failure location information from a memory-under-test (MUT) having a predetermined storage capacity is disclosed. The failure capture circuit includes failure detection circuitry adapted for coupling to the MUT and operative to apply test signals to the MUT and process output signals therefrom into failure information. The failure information is indicative of failed memory cell locations. A look-up table couples to the failure detection circuitry for storing the location information, thereby minimizing the size of the look-up table and the time to transfer failure data to a redundancy analyzer.

Z-axis pressure mount connector fixture

Abstract: An electro-optical connector is described that provides a separable electrical interface for connecting to a circuit board. The optical connection between the fiber and the connector are semi-permanent. Also described is an electro-optical system that transfers signals between two circuit board over an optical fiber where the separable interface within the system is electrical rather than optical. Further described is a fixture with pivoting actuation and retraction for connecting a z-axis pressure mount connector to a circuit board.

Lighting arrangement for automated optical inspection system

Abstract: An optical inspection system with an improved illumination system. The improved illumination system used to illustrate the invention has a base formed from a printed circuit board. Substrates for mounting lighting elements, which are exemplified by light emitting diodes, are formed also on printed circuit boards. These circuit boards have serrated edges and the diodes are mounted to the serrations. This configuration allows the light emitting elements to be focused on the focal point. Also in the exemplary illumination system, the light emitting elements have different beam widths so that variations in the illumination intensity as a function of elevation angle are reduced.

Binning of results from loop qualification tests

Abstract: The present invention provides a method and apparatus for performing line qualification tests, and binning the results of such testing. The lines are tested to determine or estimate various characteristics of the line. Physical characteristics of the line may be estimated (e.g. line length, line gauge, insertion loss). The presence of devices on the line such as load coils, bridged taps, terminations and the like may also be determined. A prediction of the data rate the loop can support is made from the measured and estimated line conditions. The results are binned according to certain criteria and to provide an easily discernable status of the line. The binning can be performed by a computer using software designed specifically for this purpose. The binned results may include a first category indicating the line cannot support a certain level of high speed access. The binned results may also include a second category indicating the line can support a certain level of high speed access. The results may also include a third category indicating the line cannot currently support a certain level of high speed access but would be able to upon removal of an impediment. A fourth category indicating the characteristics of the selected line fall outside the area of coverage of the test system may also be included. Each category may be assigned a respective color in order to make the status of the line easily discernable. The testing and binning may be performed for a variety of different high speed access levels. Customers can be charged different rates dependent upon the level of service made available to them.

Automatic test equipment with narrow output pulses

Abstract: Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.

Single carriage robotic monorail material transfer system

Abstract: A system to automate distribution of materials and tooling to production machines, where a very simple cross-section track, such as a circle or an X, is anchored to the equipment and to load/unload stations for materials and tooling, and where simple one or two wheeled robotic cars, where the wheels need not be mounted with yaw pivots to the cars, transport the materials or tooling. A control system keeps controls the motor or motors that drive one or two wheels to minimize pitch of the cars as they move along the track.

Driver with transmission path loss compensation

Abstract: A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.

Test head actuation system with positioning and compliant modes

Abstract: A system for positioning a test head for compliantly docking the test head with a prober, handler, or other peripheral for automatically testing electronic components. The system includes a plurality of backdrivable linear actuators. Each actuator has a first end mechanically coupled to the test head and a second end mechanically coupled to a support for holding the test head, for example, a manipulator. In a first mode, a control system applies inputs to the actuators for variably extending the actuators to establish a desired position of the test head relative to the support. The desired position is generally a centered position of the test head within a compliance range; however, it may also be a non-centered position that tends to align the test head with the peripheral. In a second mode, the control system stops varying the input to the actuator. The actuator tends to maintain its position, but complies with external forces applied to the test head. In the second mode, the actuators can be driven in compliance with external forces both forward and backward, and provide only slight resistance to movement in both directions. The disclosed system for positioning a test head is particularly useful for providing compliant docking with extremely heavy test heads.

Temperature control structure

Abstract: A semiconductor structure for controlling the temperature of a component is described. The structure includes a resistive layer having one or more channels provided therein and having a resistance characteristic such that a signal applied thereto causes the resistive layer to generate heat. A cooling fluid is fed through the one or more channels to cool both the structure and a component disposed on the structure. By providing the cooling channels in the resistive layer, the heating and cooling sources are intermingled. The structure can optionally include precising and vacuum clamping structures, to locate and hold the component that is to be temperature controlled.

Inspection method utilizing vertical slice imaging

Abstract: An inspection method utilizing vertical slice imaging. A number of horizontal slice images, extending through an object of interest, are acquired. A vertical region of interest is defined from the data representing the horizontal slice images. A vertical slice image is constructed based upon the horizontal slice image data falling within the vertical region of interest. The vertical slice image data may be analyzed to detect defects. In addition, a method is provided to detect defects in a BGA joint. The method includes locating a center of the joint. The method may further include measuring a number of diameters through the center of the joint and applying a rule to compare the measured diameters to an expected diameter.

DUT power supply having improved switching DC-DC converter

Abstract: A switching DC-DC converter unit is disclosed that includes an input for receiving a first DC voltage from a DC power source and switching circuitry coupled to the input to generate a switched alternating voltage from the first DC voltage. The switching circuitry includes a plurality of semiconductor switches having respective gate, source and drain leads, and further including noise suppression elements disposed on the drain leads. The unit further includes transformer circuitry coupled to the output of the switching circuitry and conversion circuitry disposed at the output of the transformer circuitry to convert the switched alternating voltage to a second DC voltage.

Modular semiconductor tester interface assembly for high performance coaxial connections

Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.