Showing papers by "Teradyne published in 2013"

Uncoordinated Cooperative Jamming for Secret Communications

Abstract: We consider a Gaussian wiretap channel model with a single-antenna source, destination and eavesdropper. The communication is assisted by multiple multiantenna helpers that transmit noise to confound the eavesdropper. First, we consider a nulling scheme, in which each helper independently transmits noise, designed to maximize the system secrecy rate while creating no interference to the destination. In this scheme, each helper requires only local relay-destination channel state information (CSI). When global CSI is available at the relays, the nulling scheme is not optimal. The optimal jamming noise structure is also provided under global CSI. Interestingly, it is shown both analytically and via simulations that, despite its reduced CSI requirements, the nulling scheme may have secrecy rate performance that is very close to the optimal one. The probability of outage of the nulling scheme is provided in closed form based on the statistics of the eavesdropper CSI.

Electronic assembly test system

Abstract: An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.

Interconnect for transmitting signals between a device and a tester

Abstract: A system includes: a circuit board including electrical elements arranged at a first pitch; a wafer including contacts arranged at a second pitch, where the second pitch is less than the first pitch; and an interconnect including additively-manufactured electrical conduits that are part of an electrical pathway between the electrical elements and the contacts, where the additively-manufactured electrical conduits include electrically-conductive material.

FPGA-based universal embedded digital instrument

Abstract: In order to test products, a multi-purpose digital instrument has been developed which can be completely embedded within on-board FPGAs. This instrument incorporates numerous features such as specialized triggering, fault capture, and pattern edge placement. To increase usability, pattern generation and protocol-aware features are included within its small footprint. The applications of the embedded instrument can include design verification, production test, and fault diagnostics in a simple and low resource implementation.

Parallel operation of system components

Abstract: An example system may include the following features: slots configured to receive devices to be tested; a device transport mechanism to move devices between a shuttle mechanism and slots; a feeder to provide devices untested devices and to receive tested devices; and a shuttle mechanism to receive an untested device from the feeder and to provide the untested device to the device transport mechanism, and to receive a tested device from the device transport mechanism and to provide the tested device to the feeder.

Executing code on a test instrument in response to an event

Abstract: Automatic test equipment (ATE) may include: a test instrument to implement a communication protocol to communicate to a unit under test (UUT), where the test instrument is memory storing bytecode that is executable, and where the test instrument being configured to identify an event in communication between the test instrument and the UUT and, in response to the event, to execute the bytecode. The ATE may also include a test computing system to execute a test program and an editor program, where the editor program is for receiving human-readable code and for generating the bytecode from the human-readable code, and the test program is for registering the event with the test instrument and for downloading the bytecode to the test instrument for storage in the memory.

Managing energy transmission

Abstract: An apparatus includes a body. The apparatus includes a test slot assembly configured to receive and to support a storage device for testing; at least one first vibration management element, disposed between the body and the test slot assembly and configured to disperse a first frequency vibrational energy. The apparatus includes at least one second vibration management element, disposed between the body and the test slot assembly and configured to disperse a second frequency vibrational energy, the first frequency vibrational energy having a first frequency that is above a second frequency of the second frequency vibrational energy.

Matrix testing targets

Abstract: An example system for testing camera modules includes: a structure for holding camera modules under test, where each of the camera modules includes an image sensor, and where the camera modules are arranged in a same plane on the structure and offset from each other in the plane; and a target for use in testing the camera modules concurrently, where the target includes multiple tiles that are repeated, where each tile contains information for use in testing a camera module, and where the camera modules and the tiles are arranged so that different camera modules face different tiles but see at least some of the same information at the same angle.

Method and apparatus for device testing using multiple processing paths

Abstract: According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.

Rotatable camera module testing system

Abstract: An example system for testing camera modules may include: a polygonal structure that is rotatable, where the polygonal structure includes faces, each of which is configured to receive at least one camera module under test; and targets facing at least some of the faces of the polygonal structure, where each target is usable in testing a corresponding camera module facing the each target.

The implementation and application of a protocol aware architecture

Abstract: System On a Chip and other highly integrated mixed signal devices have exploded in design and function complexity. New device designs exhibit non-determinism in timing, phase and data; functional blocks without a coherent shared time base; and the integration of many differing protocols and external busses. Traditional semiconductor ATE addresses these challenges with stored stimulus and response vectors and pre-planned timing, greatly increasing the difficulty of debug, lowering development productivity and reducing test coverage. The challenge is further extended by multi-site and concurrent test. Recent ideas in the development of protocol aware test methods and architectures promise to meet these challenges and introduce a new paradigm for test development. This paper will present an implementation of these ideas in a new digital channel architecture and demonstrate their application in a complete mixed signal SOC semiconductor ATE design.

Considerations in the design of a boundary scan runtime library

Abstract: IEEE 1149.1 boundary scan has become a widely used test technique since its introduction in the 1990s. Such tests are typically developed using software and hardware provided by companies that specialize in boundary scan testing. To help integrate this type of testing into large-scale military test systems, the idea of a boundary scan runtime library was introduced in 2011 and is now beginning to be adopted. Such a runtime library allows each boundary scan supplier's runtime software to apply previously-developed tests using the general purpose digital hardware in a large-scale military test system, even though those tests were initially developed using different hardware.

Automated test system with event detection capability

Abstract: A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.

Automated test system with edge steering

Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

Test scripting — An alternative approach to realtime instrument control

Abstract: In many test applications involving high speed digital data buses, the time required to receive data from a Unit Under Test (UUT), process that data, and provide a response to the UUT may be small enough to preclude use of the computer controlling the overall test system, even if the nature of that data processing is not very complex. In these situations, Test Program Set (TPS) developers can use local computing power that is embedded in a particular test instrument. However, developing test programs to run on this embedded computing power can be difficult and involve purchasing additional software tools beyond what is provided with the test system. In addition, the embedded computer program does not run independently, but rather in tandem with and under the control of, the test program running on the test system computer. So, in addition to developing the algorithms to receive, process, and transmit data, the TPS developer must also provide the framework by which the overall test program can control these operations. The solution proposed in this paper helps simplify the TPS development effort by; 1) providing a simple scripting language that TPS developers can use to create test scripts that execute on the test instrumentation, 2) providing them with tools to code and compile those test scripts, 3) providing the necessary framework for them to allow the overall test program to control the operation of the test scripts, and relieving the TPS developers of that burden, and 4) providing an alternative to them having to purchase expensive, real-time programming tools. This paper identifies test applications where test scripting may be used effectively in reducing overall TPS development time, lists basic features of a test scripting language, describes the capabilities needed of the accompanying tool set, and how the test scripts would be developed and integrated into a TPS. The paper also includes a practical example of a test script used to dynamically modify data as part of a Fibre Channel based test application.

Air circulation in a system

Abstract: An example system may include racks that house slots, in which devices may be stored for testing. Cold air from a cold atrium is drawn over the slots and expelled into a warm atrium. The resulting warm air is cooled and then recycled back through the slots to control slot temperature.

Smooth vi mode crossover method at compliance limit threshold

Abstract: Source measure units may operate as a voltage/current (V/I) source for a load, such as a device under test (DUT). Source measure units having a voltage controlled mode and a current controlled mode are described. The source measure units may have a suitable configuration to transition between the voltage controlled mode and current controlled mode in a smooth manner, and may be operated accordingly.

Verifying fibre channel FC-AV ULP functionality in a UUT

Abstract: As electronic warfare becomes more advanced, many obsolete military avionics components are being replaced with more modern components that rely on high speed busses to communicate. Among the protocols running on these high speed busses is the Fiber Channel FC-AV Upper Level Protocol. This protocol provides a means of streaming large volumes of audio and video data at high speeds over a Fiber Channel link. Due to the mission critical nature of many of these systems, maintaining system readiness through verifying these FC-AV components is vital to achieving the systems overall purpose. This paper describes a test solution for the Fiber Channel FC-AV upper level protocol implemented on a fully integrated PXI Express subsystem. This solution allows a test developer to create a test program using an application library, and execute the test on the subsystem's computer and test instrument's realtime processor. In the paper, use of the FC-AV test application library is discussed as a means of verifying the functionality of a component transmitting or receiving data over the FC-AV ULP. Particular attention is given to verification of key aspects of FC-AV traffic such as the video image data, metadata, and image refresh frequency. Methods of configuring the instruments in the subsystem to match the behavior of the unit under test through modification of the network environment at the FC-2 layer and a custom FC-AV image format are also described. Finally design tradeoffs and performance requirements considered during the development of the test solution are discussed.

Synchronizing data from different clock domains by bridges one of the clock signals to appear to run an integer of cycles more than the other clock signal

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Synchronizing data from different clock domains

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Enabling communication between ATLAS environment with an integrated subsystem

Abstract: Technology upgrades bring about the need for fielded ATLAS-based environments to expand tests to include modern high speed digital systems. The ATLAS test language does not contain innate capability to describe new tests, so TPS developers use NAM or FEP constructs as the mechanism to communicate with an external system. An external system, such as a self-contained, fully-integrated instruments within a PXIe Express chassis that includes a dedicated PC controller, is available to provide such high speed serial bus tests. While these subsystems can be integrated with an existing test system that has a Windows-based computer, additional work is needed to enable the integrated subsystem to communicate with the ATLAS operating environment. The ATLAS Host API was developed to address both needs; new or existing TPS's in the ATLAS environment are enabled to interact with a subsystem that provides new test capability, and the subsystem can use a test controller based in ATLAS. The work serves as an example that an existing test system can be extended to support new test applications, while demonstrating a client-server based architecture of a subsystem can be extended to support a new operating system in a straightforward way. This paper will describe the clientserver extension on the integrated subsystem, the ATLAS Host API executed as FEP on ATLAS, the specifics of communication of composing commands and processing responses, and some examples. This paper will also discuss the considerations behind the architecture and challenges in the development and implementation.