Showing papers by "Yeshwantrao Chavan College of Engineering published in 2014"

Unhealthy region of citrus leaf detection using image processing techniques

Abstract: Producing agricultural products are difficult task as the plant comes to an attack from various micro-organisms, pests and bacterial diseases. The symptoms of the attacks are generally distinguished through the leaves, steams or fruit inspection. The present paper discusses the image processing techniques used in performing early detection of plant diseases through leaf features inspection. The objective of this work is to implement image analysis and classification techniques for extraction and classification of leaf diseases. Leaf image is captured and then processed to determine the status of each plant. Proposed framework is model into four parts image preprocessing including RGB to different color space conversion, image enhancement; segment the region of interest using K-mean clustering for statistical usage to determine the defect and severity areas of plant leaves, feature extraction and classification. texture feature extraction using statistical GLCM and color feature by means of mean values. Finally classification achieved using SVM. This technique will ensure that chemicals only applied when plant leaves are detected to be effected with the disease.

Optimized DG placement in radial distribution system with reconfiguration and capacitor placement using genetic algorithm

Abstract: This paper presents minimization of total power loss, improvement in bus voltage profile and branch currents using network reconfiguration, capacitor banks and optimum number of distributed generation (DG) units placement in radial distribution system (RDS). Genetic algorithm (GA) is used to determine highly non-linear problem of calculating total power loss of RDS which are subjected to operational equality and inequality constraints. The effectiveness of this method is illustrated by comparing the results with Harmony search algorithm (HSA) and GA from the literature. The solution to the objective of minimization of loss is obtained using MATLAB optimization toolbox and MATLAB programming environment on standard IEEE 33-bus test system with different case studies.

Domain specific search of nearest hospital and Healthcare Management System

Abstract: Developed and developing countries have recognized the importance of Electronic Health Record in Healthcare Management System. Emergency Medical System (EMS) is a revolutionary approach to emergency medical treatment in some medical emergency. It also describes a mobile system that enables electronic healthcare data storage, update and retrieval using Cloud Computing. It observed that people in unknown area are in severe danger if they don't able to find hospital quickly. In emergency case a single minute counts so it is very important that automatic applications must be used for decision making, maintain up to date status of the hospital. Saving the time which can be save life of the patient. When the doctor or family receives the alarm message, they can immediately take measures to rescue the user. It can also manage the health record of the user. The user can take online medical to send their physical condition and then get prescription from doctor who will send the prescription on the user's phone. The proposed system locates nearest available hospital, contacts its ambulance emergency system, accesses a Electronic Health Record of emergency patient that can critically assist in pre-hospital treatments. The system will identify availability of the nearest available specialized hospital all through EMS server which provides continuous information about the incoming patient to the hospital. This paper proposes Android Based Tracking for EMS (Emergency Medical System) on cloud.

Design and simulation of new XOR gate and code converters using Quantum Dot Cellular Automata with reduced number of wire crossings

Abstract: Quantum Dot Cellular Automata is one of the six emerging technology which can overcome the limitations of current transistor based technology. Quantum Dot Cellular Automata is popular technology due to its extremely small feature size and ultra low power consumption. In this paper new XOR gate using Coupled Majority Voter Minority gate is proposed. Using this proposed XOR gate Binary to Gray Code and Gray to Binary Code Converters are designed. This paper shows the performance analysis of Proposed XOR circuit and it has been proved that XOR gate and Binary to Gray and Gray to Binary Code converters are efficient in terms of area, complexity, latency and wire crossings. QCADesigner 2.0.3 tool is used for design and simulation of these circuits.

Identification of critical success factors for quality-productivity management approach in different industries

Abstract: Rapid industrialisation has demanded that the processes that govern quality and productivity be developed at a similar rate, however, quality management approaches have lagged behind and remain a constant case for investigations. In view of this, the role of critical success factor (CSF) identification has been of very high importance. This study has attempted to study the approach of past researchers in identifying the CSFs of total quality management (TQM). Standard methodology was followed to review the published literature. The results indicated that the critical review of literature is the most highly adopted approach and case studies have received relatively less attention. Though the survey was carried out for small, medium, large-scale manufacturing and the service industry, it was apparent from the literature that the integration of various CSFs of TQM can help the manufacturing industries in sustainable quality improvement with the TQM approach. The various CSFs identified for industries are top managements’ commitment; continuous improvement; working environment; stakeholders’ involvement; quality tools; strategy, policy and planning; information and communication management; employee involvement and empowerment; process monitoring and production development; suppliers’ involvement and management; customer involvement and satisfaction; training and development; and support to employees.

Evaluating green manufacturing drivers: an interpretive structural modelling approach

Abstract: Green manufacturing (GM) is a sustainable method of manufacturing that minimises waste and pollution. GM covers the entire product life cycle from conceptual design to disposal in a benign, harmless manner. It causes no or minimal adverse impact on environment by optimum use of resources and reduction of waste and pollution. 4R’s (reduce, reuse, recycle, remanufacture) is slowly being accepted and adopted as the model of growth and sustainability the world over. Its implementation is supported by few factors which are known as GM drivers. There are many drivers which are expanding the boundaries for green manufacturing. These drivers could facilitate to adopt Green manufacturing. The aim of this paper is to develop a relationship amongst the identified GM drivers; including management commitments, regulatory pressure, pressure from stakeholders etc. This paper is also helpful in understanding mutual influences of drivers. It helps in identifying those drivers which support other drivers as well as those drivers which are most influenced by other drivers (dependent) using interpretive structural modelling (ISM) and it classifies these drivers depending upon their driving and dependency on power.

Line commutated converter for grid interfacing of solar photovoltaic array

Abstract: The line commutated converter (LCC) is matured technology which is used for power conversion. The LCC is tied to a grid in which commutation of power devices (SCR) is achieved by grid voltage. In this paper, three phase LCC in an inverter mode is proposed for interfacing of solar photovoltaic (PV) array and ac grid. This topology does not require to make and maintain the synchronism between converter and ac grid. In addition, it follows maximum power point tracking (MPPT) of solar PV array by changing the firing angle of LCC. The simulation and experimental results demonstrate the feasibility of the proposed solution.

Wavelet based transmission line fault classification and location

Abstract: Now a days the demand of electrical energy continuously increasing day by day, to fulfill this demand the electrical power network becomes complicated. Wavelet analysis which is a mathematical tool for signal analysis is used to detect and classify the type of fault occurring on the transmission line. This paper presents an improved algorithm for transmission line fault classification by using wavelet. Use of Impedance measurement technique and travelling wave theory is adopted here for the location of fault. Discrete wavelet transform of current signals is utilized for fault classification. MATLAB/Simulation is used to generate fault signals. Simulation results reveal that the performance of the proposed fault detection indicator is promising and easy to implement for computer relaying application.

Novel cryptographic algorithm based fusion of multimodal biometrics authentication system

Abstract: Currently Security for every organization is a bigger challenge Conventional security systems have lot of drawbacks that need to be addressed The use of Biometrics in security systems is current trend We propose a framework of fusion and encryption of multimodal biometrics authentication system In this two Unimodal traits Iris and Fingerprint is used collectively for generation of secure cryptographic template The process is categorized into three modules 1) Pre-processing of acquired iris and fingerprint, 2) Extraction of discriminable Features, 3) cryptographic Multimodal biometric template generation Initially, the preprocessing are perform separately for iris and fingerprint Followed by the minutiae point's extraction from Fingerprint, which includes termination, bifurcation, and angle of orientation of each point respectively Subsequently, the iris features are extracted using wavelet transform Then feature level fusion is performed Finally, a 120bit secure cryptographic template is generated from the multi-biometric template We test our results on standard iris CASIA database and the real Fingerprint captured in our own college The several experimental results demonstrate the effectiveness of the proposed approach Also the security of biometric template is improved with the help of encryption

Control of D-STATCOM under unbalanced and distorted voltages using Synchronous Detection method for load compensation

Abstract: This paper presents Distribution Static Compensator (DSTATCOM) configuration in three phase four wire system, using three level Neutral Point Clamped (NPC) inverter operated in current control mode for load compensation to enhance the quality of power. The behavior of shunt compensator is analyzed using Synchronous Detection method. The purpose of this compensating scheme is to provide completely balanced and sinusoidal source currents under unbalanced and distorted source conditions. The chosen control algorithm includes three different approaches-equal current, equal power and modified equal current. The above said criteria are compared graphically and analytically for unbalanced and non-linear load condition. Results obtained show that modified equal current approach is more effective than the other two even if the source voltages are severely distorted and unbalanced. For realization, an extensive digital simulation is done using MATLAB environment.

WiMAX network based E health service and telemedicine applications for rural and remote populations in India

Abstract: In India, today also remote villages are out of mobile network coverage because of private service providers are not willing to deploy the mobile network in remote rural area because of less chance for revenue generation. BSNL is providing WiMAX broadband connectivity only for cities and town and remote villages are waiting for high speed broad band connectivity to access E. services. Over all rural health is in poor stage due to unavailability of modern technology, ICT infrastructure, E. health services, telemedicine, sufficient doctors to monitor health. In case of any disaster, Epidemic diseases there are no national health insurance policy for the country. Government supported healthcare delivery follows a three tier system and is the primary responsibility of each state. It has been observed that there is a great deal of disparity in quality and access to healthcare between urban and rural regions. This can be bridged through telemedicine technology based on WiMAX Broadband connectivity if the tool is integrated into existing healthcare delivery system. Both government and private sector have been actively participating in tele-health programmes. The telemedicine market has witnessed spectacular growth during the last two years mainly because of timely convergence in the areas of Information technology, Communication and Healthcare along with launching of central e-health schemes including telemedicine by the Ministry of Health and Family Welfare.

Design and implementation of single electron transistor N-BIT multiplier

Abstract: The ancient method of multiplication with low power device i.e. Single electron transistor is used for designing is presented in this paper. SET which is low power device is used to produce new innovations, which is not possible to achieve with only CMOS circuit. The very innovative & simple method of multiplication is presented. By this method of multiplication, n-bit multiplication becomes simple with low power. The basic & circuits required for this design i.e. AND Gate, Half Adder, Full Adder is designed & simulated. 3-bit Multiplier is designed & simulated. For simulation a Spice is used. The logical operation of 3-bit multiplier is explained & verified theoretically as well as by simulation. The Single Electron Transistors is nano device and have less power consumption as compared to CMOS.

Measurement of retinal thickness for detection of Glaucoma

Abstract: The thickness of retinal nerve fibre layer (RNFL) is one of the parameters for assessing the Glaucoma. It is second largest disease which causes blindness. Glaucoma is caused due to the increase of intra ocular pressure (IOP). Vision is lost before the patient becomes aware of glaucoma. Optical Coherence Tomography (OCT) provides enhanced depth and clarity of viewing tissues with high resolution compared with other medical imaging device such as fundus camera or intravascular imaging. This paper presents an automatic method to find the thickness of RNFL using OCT images. The proposed algorithm first extracts all the layers present in the retina using Sobel operator and an algorithm is then developed. The thickness measurement of RNFL is automatically displayed based on pixel calculation. The calculated thickness values are compared with the original values obtained from hospital. The result shows that the proposed algorithm is efficient in segmenting the region of interest without manual intervention. The effectiveness of the proposed method is proved statistically by the performance analysis.

Reliability of different levels of cascaded H-Bridge inverter: An investigation and comparison

Abstract: This paper presents the comparative analysis of reliability of different levels of cascaded H-Bridge inverter topologies. Failure of single IGBT in a cell of H-Bridge can determine the reliability of the complete cell. Military Handbook-217F provides basis for computation of reliability of semiconductors. This method is not applicable for reliability evaluation of IGBT. To determine the temperature cycles of IGBT, thermal impedance model is developed and power cycles are obtained by using transfer function in MATLAB simulation. By Coffin-Manson fatigue life relationship, the number of temperature cycles is detected by MATLAB programming. An algorithm is used to correlate number of temperature cycles with failure rate. Mean time to failure (MTTF) of each model is compared. It was observed that reliability increases with increase in number of levels of multilevel inverter.

Improved fused floating point add-subtract and multiply-add unit for FFT implementation

Abstract: This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules in terms of area, delay, power and energy. Here we have achieved reduction in area (in terms of LUT required) by 27.09%, reduced delay by 7.10%, reduction in power consumption by 11 % and energy is reduced by 26.22% as compared to discrete implementation.

An instrument for identification of critical factors for quality and productivity improvement in sponge iron industry

Abstract: Sponge iron (SI) industry is relatively new and presently passing through teething problems. For higher and higher production, quality and productivity (Q&P) is always ignored. However, this approach has led to making the problem worse. Implementation of total quality management (TQM) can help solve the problems similar to other industries. But extensive literature review indicates that no study has yet identified and statistically established the reliability and validity of a set of critical success factors (CSFs) for implementation of TQM for Q&P improvement in SI industry. Implementation of TQM needs a validated instrument. This work aims to fulfil this gap. Through extensive literature analysis, the authors have identified a number of attributes and CSFs of TQM of various sectors. With the help of judgmental selection of attributes, an instrument was developed and a pilot study was carried out in SI units in a small region in India to validate the instrument. This validated instrument could be used for study on a wider scale for the development of a generalised model for SI industry. With little modification, the instrument can also be used for other process industries. The research is unique and a primary step towards reaching the needs of SI industry i.e., Q&P improvement through TQM implementation.

Design and implementation of artificial magnetic conductor structure along with feed line for microstrip patch antenna array

Abstract: This paper presents new design of artificial magnetic conductor structure along with feed line. 4 × 1 microstrip patch antenna array using AMC improves performance of antenna. AMC structures are used in design low profile antennas. High gain, minimum size and larger band width required for communication system. This leads to design patch antenna array. So this paper presents four element microstrip patch antenna array with artificial magnetic conductor structure. It uses FR4_epoxy as dielectric substrate. 4 × 1 microstrip patch antenna array is designed using HFSS simulation software. Simulation and measured results are compared.

HDL implementation of 128- bit Fused Multiply Add unit for multi mode SoC

Abstract: Binary 128 arithmetic finds a hard in floating point application of Quadruple Precision. The major component of 128 bit Fused Multiply Add (FMA) unit with multimode operations are Alignment Shifter, Normalization shifter, Dual Adder by CLA. The main contribution of this paper is to reduce the latency. The technical challenges in existing FMA architectures are latency and higher precision. The precision gets affected by the repeated occurrence of fractional part. In order to reduce the latency the dual adder is designed by using compound Adder and the latency of overall architecture gets reduced up to 30-40%. In this paper the total delay of dual adder designed using compound adder is found to be 5.776 ns. Simultaneously to get higher precision we design namely Alignment Shifter and Normalization Shifter in the FMA unit by using Barrel Shifter as this Alignment Shifter and Normalization Shifter will have less precision, but since replacement of these blocks by Barrel Shifter will result into higher precision.

Floating Point-based Universal Fused Add–Subtract Unit

Abstract: This paper describes fused floating point add–subtract operations and which is applied to the implementation of fast fourier transform (FFT) processors. The fused operations of an add–subtract unit which can be used both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating point operations. When placed and routed using a high-performance standard cell technology, the fused FFT butterflies are about may be work fast and gives user-defined facility to modify the butterfly’s structure. Also the numerical results of the fused implementations are more accurate, as they use rounding modes is defined as per user requirement.

The design approach for fast computation of fourier transform over a finite field

Abstract: The Fast Fourier Transform can be determined in Complex field and Galois field. The paper suggests the algorithm for finding Fast Fourier Transform over a Galois field. This method uses the advantage of cyclotomic decomposition. Basically decomposition of the original polynomial into a sum of linearized polynomial is done and then evaluated at a set of basis points. The idea of architecture is also proposed. The architecture is composed of two main units principle unit and additional unit. This Fast Fourier Transform methods can be capably used in implementations of discrete Fourier transforms over finite field, which have extensive applications in cryptography and error control codes. The method is becoming popular because of its low computational complexity.

Improved fused floating point add-subtract unit for FFT implementation

Abstract: This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules in terms of area, delay, power and energy. Here we have achieved reduction in area (in terms of LUT required) by 27.09%, reduced delay by 17.10%, reduction in power consumption by 11 % and energy is reduced by 26.22% as compared to discrete implementation.

Implementation of adaptive filter for channel estimation

Abstract: Adaptive Channel Estimator is a most important research topic in wireless communication. Here we have to reduce the error from the received signal which may be corrupted by the environmental reason or due to the multipath fading. In this paper we are concentrated more on the hardware implementation of Adaptive filter using LMS algorithm which has been synthesized within FPGA. In this paper our main aim is to implement the LMS core in FPGA by using VHDL code and observe its synthesis and simulation result.

Design of Trellis code modulation decoder using Hybrid Register Exchange Method

Abstract: This paper presents the technique for designing the area efficient trellis code modulation encoder and decoder. One of the best encoding techniques is convolutional encoding as convolutional encoding improves the error performance of communicational channel. The trellis code modulation (TCM) can achieve the better error performance without Bandwidth expansion. Viterbi decoder is use in Trellis code modulation, to decode a data which is encoded by a convolutional encoder. Here TCM encoder and decoder are designed by using Xilinx ISE 13.2 design software and device use is Spartan 6. Proposed technique is aims to reduce the hardware requires for designing the TCM decoder by using hybrid register exchange method. Hybrid register exchange method (HREM) is a combination of the register exchange method (REM) and Traceback (TB) technique. HREM is superior as compared to Register Exchange Method (REM) and Traceback method (TB), where area requires for designing of survivor memory unit is more as compare to the proposed technique.

Power reduction in network on chip links

Abstract: Network on chips structure makes a fitting replacement for system on chip designs in designs incorporating large number of processing cores. In network on the major source of power dissipation is the network on chip links. If compared the power ratio between the network on chip links and router links are more power hungry than router. The dynamic power dissipation in links is major contributor to the power consumption in network on chip. This is due to the self switching and the second factor is cross coupling capacitance. In the proposed encoding technique the first self switching is reduce by checking the switching transition and then the coupling between the links is checked and ensured that the power consumption is reduced. This encoding technique is incorporated with the wormhole routed network. The end to end scheme incorporating the encoding technique to reduce power in the wormhole routed network on chip. The encoder and decoder of the proposed scheme with wormhole router are described in the RTL level in verilog HDL.

Evolution of Ultra Wide-Band Swastik Shaped Monopole Antenna for Cognitive Radio Applications

Abstract: The proposed antenna designed specifically for Cognitive radio applications consists of a circular monopole which is evolved into the Swastika shaped dotted monopole by incorporating slots into the plane circular monopole which enhances the band width as well as gain. This ultra-wideband sensing antenna covers the spectrum from 3.425 GHz - 14.99 GHz [11.53GHz] with a gain of 6.18dBi as against 10.56GHz bandwidth of plane circular monopole with a gain of 2.17dBi. Simulated results are presented and find in good agreement with the expected results.

A 10-bit 25MSPS low power pipeline ADC for Mobile HDTV Receiver System

Abstract: This paper describes a 10-bit 25MSPS analog-to-digital converter (ADC) for Mobile HDTV Receiver System. The ADC is based on a 4-3-3 bits- per-stage pipeline architecture and The proposed pipelined ADC adopts a optimized stage resolution based on power consumption of sample and hold circuit and comparator. At the target sampling rate of 25MS/s, measured results show that the converter consumes 12.36mW from a 1.8V power supply and 56dB SNR and 60dB SFDR.

Simulation of two phase matrix converter for driving a two phase induction motor

Abstract: This Paper describes a method of generating two phase supply for two phase inductor motor The novelty of scheme is a simple algorithm and the scheme can be fabricated as integrator chip iS2MC Matrix converter (MC) technology is already used in industrial applications, but is limited to three-phase induction motor with three-phase power line It has no limit on output frequency due to the fact that it uses semiconductor switches with controlled turn-off capability The circuit which consists of 8 bidirectional switches, enables a two-phase induction motor to be driven by single-phase power line without smoothing capacitors The MC generates independent two-phase voltages controlled by a simple switching algorithm, Two-phase motor driven by MC eliminates start-run capacitors and generates more torque than the three-phase motor The performance of the system with symmetrical two-phase induction motor was confirmed by simulation

Novel fault attack resistant Elliptic Curve processor architecture

Abstract: Fault attacks on Elliptic Curve Cryptosystems have drawn considerable attention. This paper improves fault attack resistant architecture for Elliptic Curve Cryptosystems proposed by Agustin Dominguez et al. using point validation module. Proposed architecture improves the architecture by adding time shared Point Validation module, Zero-One detector and comparator module. The proposed architecture prevents fault, saves computation time and resists revealing of the secret key information. Proposed architecture is implemented on Xilinx Virtex-6 platform. Area is decreased by 5.61% as we have used time shared point validator unit. Also, power is saved by 18.27%.