Showing papers in "IEEE Transactions on Circuits and Systems in 2007"

CNTFET Modeling and Reconfigurable Logic-Circuit Design

Abstract: This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

A Programmable 210-μV Offset Rail-to-Rail G m -C Filter.

Abstract: Low input-referred offset performance and linearity in analog filters are critical design parameters, yet transistor mismatch limitations are a severe hindrance. Programmability is also a feature of growing significance because high performance state-of-the-art systems must adapt on-the-fly to various operating conditions, as is the case in battery-operated electronics where systems traverse through idle, alert, and high performance modes in an effort to conserve energy and extend battery life. This paper presents a continuous and programmable first-order GM-C filter with sub-milli-Volt offset performance. Low offset is achieved by auto-zeroing and continuity by pingponging between two transconductors, all under the construct of a compact and bandwidth-efficient circuit topology. The proposed GM-C circuit was fabricated with AMI’s 0.5-μm CMOS process technology and achieved an input-referred offset of less than 210 μV, hand-over glitches of less than 40 mV, and 57 dB of linearity over the rail-to-rail input span for a lithium-ion battery supply range of 3 to 4.2 V. The bandwidth and gain of the filter were programmable from 1.1 to 6.5 kHz and 1.27 to 29.1 V/V, respectively, both with better than 3.2% resolution.

Fast Matching Pursuit Video Coding by Combining Dictionary Approximation and Atom Extraction Design

Abstract: In this paper, we propose a systematic approach that approximates a target dictionary to reduce the complexity of a matching pursuit encoder. We combine calculation of the inner products and maximum atom extraction of a matching pursuit video coding scheme based on eigendictionary approximation and tree-based vector quantization. The approach makes the codec design and optimization cleaner and more systematic than previous dictionary approximation methods. We vary the quality of approximation to demonstrate the tradeoff between computational complexity and coding efficiency. The experiment results show that our codec achieves speed-up factors of up to 100 with a performance loss of less than 0.1 dB. We use double-stimulus impairment scale scores to evaluate the perceptual quality of our approach for different levels of complexity.

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

Abstract: In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR). In this paper, a hardware-oriented fast algorithm is proposed with the intra-/inter-candidate DR considerations. In addition, based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles. According to the implementation results, 97% computational complexity is saved by the proposed fast algorithm. In addition, 77.6% memory bandwidth is further saved with the proposed DR techniques at architecture level. In the ultra-low-power mode, the power consumption is 2.13 mW for real-time encoding CIF 30-fps videos at 13.5-MHz operating frequency

Authors' Reply [to "Corrections and Comments to 'Model Reduction of Discrete Linear Systems Via Frequency-Domain Balanced Structure'"]

Abstract: For original paper, see N. L. Prajapathy et al., ibid, vol. 54, no. 3, pp. 682-683, (2007). Reply to the comments on model reduction technique for discrete linear time invariant systems are presented. The proposed technique is based on a conceptual view point of the controllability and observability Grammians balancing of a system in an arbitrary frequency range. It can be considered as the generalization of the Moore's (1981) balance structure approach in a specific frequency range of operation. Two modified Lyapunov equations are derived for the proposed frequency domain balancing. The transfer function of the sixth-order Cheby-shev type 1 filter is considered. The Nyquist plots for the original filter as well as the reduced-order filters based on the Moore's balanced technique and the proposed method.