Showing papers in "Vlsi Design in 1997"

Combining Technology Mapping With Layout

Abstract: Due to the significant contribution of interconnect to the area and speed of today's circuits and the technological trend toward smaller and faster gates which will make the effects of interconnect even more substantial, interconnect optimization must be performed during all phases of the design. The premise of this paper is that by increasing the interaction between logic synthesis and physical design, circuits with smaller area and interconnection length, and improved performance and routability can be obtained compared to when the two processes are done separately. In particular, this paper describes an integrated approach to technology mapping and physical design which finds solutions in both domains of design representation simultaneously and interactively. The two processes are performed in lockstep: technology mapping takes advantage of detailed information about the interconnect delays and the layout cost of various optimization alternatives; placement itself is guided by the evolving logic structure and accurate path-based delay traces. Using these techniques, circuits with smaller area and higher performance have been synthesized.

Effective Coupling between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits

Abstract: Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit area and delay during layout. An algorithm for computing logic equivalence classes and performing net swapping using the equivalence classes during layout is described. Lastly, it shows the sensitivity of post-layout delays of circuits to wiring models used in synthesis and demonstrates how resynthesis techniques can be effectively used to generate good post-layout implementation. Significant reductions in post-layout area and delay on several industrial designs have been observed.

RT Component Sets for High-Level Design Applications

Abstract: The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. In this paper, we motivate the need for such a standard RT component set, and describe a library environment that supports automatic model generation, design reuse, and synthesis with technology-specific estimators. We demonstrate the efficacy of the standard RT-component set approach with experiments performed on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead of about 10% in using these standard, generic components. We then describe an automatic model generation and technology projection scheme that uses fast (on-line) estimators for predicting the area and delay of generic RT components tuned to a particular technology library with an accuracy of 10%. These model generators and estimators have been integrated with a high-level synthesis system at U.C. Irvine.

IDDQ Detectable Bridges in Combinational CMOS Circuits

Abstract: Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f-redundancy has been evaluated on a set of benchmark circuits.

Taking Thermal Considerations into Account during High-Level Synthesis

Abstract: Submicron feature sizes result in designs in which power density is significantly increased. High-level synthesis strategies are proposed in this paper to relieve potential thermal problems. Operators are placed as close as possible to their data predecessors in order to minimize the interconnection cost while not violating the thermal constraints. Spreading overused functional units away from the thermal problem area often results in performance degradation. Introducing redundant operators is suggested to reduce the module utilization and hence thermal problems among problem modules when system performance is important. Our experimental results show that this technique produces quite satisfactory results for a powerdominated example.

IDDQ Testing Experiments for Various CMOS LogicDesign Structures

Abstract: In this paper, we present two studies. The first study constitutes an assessment of the effectiveness of IDDQ (quiescent power supply current) in detecting transistor-level defects for three CMOS logic design styles. This study was carded out by designing, simulating, fabricating, and testing CMOS devices with built-in defects. The second study involves an assessment of IDDQ in a production-type environment and the effect of bum-in on IDDQ levels. This study was carried out in a production facility. The results show that IDDQ testing can detect some types of defects in precharge and pseudo-NMOS circuits but may require partitioning circuitry for the latter.

Operational and Test Performance in the Presence of Built-in Current Sensors

Abstract: The effects of Built-In Current Sensors (BICS) on I D D Q measurements as well as on the performance of the circuit under test are considered. Most of the Built-In Current Sensor designs transform the ground terminal of the circuit under test into a virtual ground. This causes increases in both propagation delay and I D D Q sampling time with the increase in the number of gates, affecting both test as well as operational performance. The effects that current sensors have on the operational and test performance of a circuit are considered. Circuit partitioning may be used for overcoming the effects of BICS on I D D Q measurements as well as on the performance of the circuit under test.

Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits

Abstract: This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Abstract: Accurate design descriptions during synthesis allow efficient use of resources. The appropriate use of distinct implementations of RTL operators helps generate optimal VLSI designs. The system presented here utilizes libraries composed of multiple modules with identical functionality, but distinct performance and area characteristics. Such libraries allow the generation of an accurate estimate of the area and delay of the final design during synthesis. Full use of the module selection capability is possible by allowing the user to specify a total area limit rather than a detailed allocation. Consequently, tradeoffs between different allocations can be fully explored. Scheduling, module selection, and allocation are performed simultaneously to achieve optimal use of area and delay, and to facilitate the incorporation of lower level design considerations into behavioral synthesis. Synthesis decisions are made in a time-constrained and area-constrained fashion, by using both constraints to identify and avoid infeasible design possibilities. Module selection, scheduling, and allocation for pipelined designs is also implemented. Experimental results show that the use of module selection and time-and-area-constrained synthesis results in an area/delay design curve which is superior to the results of traditional systems.

Layout Modeling and Design Space Exploration in PSS1 System

Abstract: This paper presents the design methodology used in PSS1, a high level synthesis system designed for computation dominated applications. It includes a behavior synthesizer and an area optimizer. Based on a pre-defined architecture, the behavior synthesizer translates a description into a number of designs with different delays and hardware costs. Based on a two-level layout model, the area optimizer fine-tunes the physical design using the information feedback from the layout tools. All the tools are linked by an X-window interface in which users can traverse among different tools and interactively change the design parameters. The output is linked to Lager system [7], a silicon assembler. The layout model allows a designer to interactively merge/split modules, change the shape of modules, and define the pin positions of modules. Experiments show that a considerable area improvement has been achieved using this methodology.

Statistical Module Level Area and Delay Estimation

Abstract: The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.

Datapath Optimization Using Layout Information: An Empirical Study

Abstract: Most datapath synthesis approaches use a simple area model to evaluate design area quality. However, using such a simplified model could mislead synthesis tasks into generating inferior designs. This paper presents an extensive experimental study to validate the correlation between the tradition area model, our proposed area model, and the actual layouts. The results show that traditional area quality measures are not good indicators for optimization in datapath synthesis. Moreover, this paper also shows that to provide accurate indications for design tradeoffs in high-level synthesis, the fidelity of the estimates is more important than the accuracy.

VLSI Testing for High Reliability: Mixing IDDQ TestingWith Logic Testing

Abstract: In this paper, we examine the effectiveness of combined logic and I D D Q testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and I D D Q testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and I D D Q test. Also, the results of I D D Q based test sets (vectors generated specifically for I D D Q testing) are compared with that of stuck-at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridging faults in I D D Q testing.