Patent
A fast fourier transformation computing unit and fast fourier transformation computation device
Tsukasa c,Motomu C,Naokatsu C +2 more
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TLDR
In this paper, the smallest possible circuit size is provided for FFT computing units, FFT computation devices, and pulse counters that can achieve computational precision using the smallest available circuit size.Abstract:
To provide FFT computing units, FFT computation devices, and pulse counters that can achieve computational precision using the smallest possible circuit size. FFT computing unit 602 comprises a data shift circuit for standardizing FFT computation target data to a specified bit width, adders/subtracters, multipliers, and data converters for standardizing the bit width to a certain bit width by truncating part of the output data of each computing unit, etc. FFT computation device comprises FFT computing unit 602, sensor 620, amplification circuit 621, gain control circuit 623, AD converter 622, first RAM 625 for sequentially storing the A/D conversion data, second RAM 626 for storing the FFT computation target data and the data being computed, coefficient ROM 101, and level determination circuit 624; and the level determination circuit determines the size of the data being transferred when the data is being transferred from RAM 1 to RAM 2, and the result is used for the data shift adjustment and gain control during FFT computation.read more
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References
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Patent
Floating-point data rounding and normalizing circuit
TL;DR: In this paper, a floating-point data rounding and normalizing circuit comprises a shift controller receiving a fraction portion of an input floating point data for generating a shift control signal indicative of a shift amount required for normalization, and an encoder is provided to generate a two's complement of a binary number indicating the above mentioned required shift amount.
Patent
Method of performing real input fast fourier transforms simultaneously on two data streams
TL;DR: Simultaneous FFT's are calculated for two real input sequences utilizing a two channel recursive FFT structure in this paper, where the method of operating such a structure disclosed includes the log 2 N stages (for an N-point transform) known in the prior art plus a final unscrambling stage.
Patent
Fast fourier transform (FFT) addressing apparatus and method
TL;DR: In this paper, an approach for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is presented, which includes a butterfly counter for determining the current FFT butterfly being computed, and an adder circuitry coupled to the incremental circuitry adds the incremental number and a plurality of memory addresses.
Patent
Method and apparatus for sequencing addresses of a fast fourier transform array
TL;DR: In this paper, an apparatus and method for generating a specific sequence of addresses of values of an array stored in a digital memory is presented, where the addresses are generated by a first counter which generates a seed value and a second counter which produces a control value, the control value controlling a bit inserter and a programmable shifter.
Patent
Continuously updating fourier coefficients every sampling interval
TL;DR: In this article, a method and apparatus for continually producing updated Fourier coefficient values of an input signal during each sample time is presented. But the Fourier coefficients are not updated for each new sample.