Proceedings ArticleDOI
A neural network implementation of an input access scheme in a high-speed packet switch
M. Mehmet Ali,H.T. Nguyen +1 more
- pp 1192-1196
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TLDR
A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented and the form of the energy function, its optimized parameters, and the connection matrix are given.Abstract:
A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each output; thus, in an (n*n) switch there will be n/sup 2/ input queues. Using synchronous operation, at most one packet per input and output will be transferred at every slot. A neural network maximizing the throughput of this switch is determined, and the form of the energy function, its optimized parameters, and the connection matrix are given. Simulations with random inputs have yielded results close to optimal throughput. This neural network can be implemented with the existing technology for medium switching sizes. >read more
Citations
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Journal ArticleDOI
The iSLIP scheduling algorithm for input-queued switches
TL;DR: This paper presents a scheduling algorithm called iSLIP, an iterative, round-robin algorithm that can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware, and describes the implementation complexity of the algorithm.
Journal ArticleDOI
Achieving 100% throughput in an input-queued switch
TL;DR: This paper introduces two maximum weight matching algorithms: longest queue first (LQF) and oldest cell first (OCF), which achieve 100% throughput for all independent arrival processes.
Proceedings ArticleDOI
Achieving 100% throughput in an input-queued switch
TL;DR: This paper proves that if a suitable queueing policy and scheduling algorithm are used then it is possible to achieve 100% throughput for all independent arrival processes.
Fast Switched Backplane for a Gigabit Switched Router
TL;DR: The Tiny Tera; an all-CMOS Terabit-per-second network switch is currently building by Nick McKeown, a professor of electrical engineering and computer science at Stanford University, which combines the analysis and design of cell-scheduling algorithms, memory architectures and the economics of the Internet.
Journal ArticleDOI
Neural networks for switching
TL;DR: The author argues that a strong impetus for using neural networks is that they provide a framework for designing massively parallel machines and presents two switching applications in which neural networks can solve the problems efficiently.
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Neurons with graded response have collective computational properties like those of two-state neurons
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