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Open AccessJournal ArticleDOI

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

TLDR
An overview of the scientific literature on timing verification techniques for multi-core real-time systems is provided covering four main categories: full integration, temporal isolation, integrating interference effects into schedulability analysis, and mapping and allocation.
Abstract
This survey provides an overview of the scientific literature on timing verification techniques for multi-core real-time systems. It reviews the key results in the field from its origins around 2006 to the latest research published up to the end of 2018. The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems. A detailed review is provided covering four main categories: full integration, temporal isolation, integrating interference effects into schedulability analysis, and mapping and allocation. The survey concludes with a discussion of the advantages and disadvantages of these different approaches, identifying open issues, key challenges, and possible directions for future research.

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https://doi.org/10.1145/3323212





Citations
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Proceedings ArticleDOI

A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling

TL;DR: A fine-grained analysis of the memory contention experienced by parallel tasks running on a multi-core platform is proposed, formulated to bound the memory interference by leveraging a three-phase execution model and holistically considering multiple memory transactions issued during each phase.
Journal ArticleDOI

Multi-core Devices for Safety-critical Systems: A Survey

TL;DR: Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality.
Proceedings ArticleDOI

E-WarP: A System-wide Framework for Memory Bandwidth Profiling and Management

TL;DR: The Envelope-aWare Predictive model (E-WarP) as mentioned in this paper analyzes the memory demand of applications following a profile-driven approach, makes realistic predictions on the temporal behavior of workload deployed on CPUs and accelerators, and performs saturation-aware system consolidation.
Proceedings ArticleDOI

Modeling Cache Coherence to Expose Interference

TL;DR: This paper proposes a nascent framework relying on timed automata to model and analyze the interference caused by cache coherence, which is hard to predict and leading to the mechanisms being shunned by real-time system designers.
Journal ArticleDOI

Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration

TL;DR: In this paper , the authors propose a holistic framework to help designers partition real-time applications on heterogeneous platforms with hardware accelerators, which is inspired by a realistic setup of an advanced driving assistance system presented in the WATERS 2019 Challenge by Bosch.
References
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Book ChapterDOI

International Organization for Standardization

Anne Marsden, +1 more
TL;DR: An overview of the International Organization for Standardization (ISO) can be found in this paper, where the authors describe the ISO standards most relevant in a clinical laboratory service setting, as well as the process for obtaining and maintaining ISO certification.

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TL;DR: The provided compressed bitstreams were uncompressed using provided software and the resulting sequences were compared to the original ones in terms of PSNR and it seems that last frames from some cameras give significantly worse PSNR than the rest of frames.
Journal ArticleDOI

A survey of hard real-time scheduling for multiprocessor systems

TL;DR: The survey outlines fundamental results about multiprocessor real-time scheduling that hold independent of the scheduling algorithms employed, and provides a taxonomy of the different scheduling methods, and considers the various performance metrics that can be used for comparison purposes.
Book

Modern Processor Design: Fundamentals of Superscalar Processors

TL;DR: This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better processor performance that have been proposed and implemented in real machines.