A systolic 2-D convolution chip

TLDR: A chip for performing the 2-D (two-dimensional) convolution in signal and image processing that consists of essentially only one type of simple cells, which are mesh-interconnected in a regular and modular way, and achieves high performance through extensive concurrent and pipelined use of these cells.

Abstract: : This paper describes a chip for performing the 2-D (two-dimensional) convolution in signal and image processing. The chip, based on a systolic design, consists of essentially only one type of simple cells, which are mesh-interconnected in a regular and modular way, and achieves high performance through extensive concurrent and pipelined use of these cells. Denoting by u the cycle time of the basic cell, the chip allows convolving a kxk window with an nxn image in O(sq m)(u/k) time, using a total of cu k basic cells. The total number of cells is optimal in the sense that the usual sequential algorithm takes O(sq m)(sq k)(u) time. Furthermore, because of the modularity of the design, the number of cells used by the chip can be easily adjusted to achieve any desirable balance between I/O and computation speeds. (Author)