Patent
Apparatus for sampling instruction operand and result values in a processor pipeline
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TLDR
In this paper, an apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, and instructions are fetched into a first stage of the pipeline.Abstract:
An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a particular selected instruction. Values of results computed during the processing of the particular selected instruction are recorded in a sampling record along with state information identifying the particular selected instruction. Software is informed whenever the particular selected instruction leaves the pipeline to read the recorded values and state information.read more
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References
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Proceedings ArticleDOI
Simultaneous multithreading: maximizing on-chip parallelism
TL;DR: Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multi-threading, and is an attractive alternative to single-chip multiprocessors.
Proceedings ArticleDOI
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
TL;DR: This paper presents an architecture for simultaneous multithreading that minimizes the architectural impact on the conventional superscalar design, has minimal performance impact on a single thread executing alone, and achieves significant throughput gains when running multiple threads.
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System for analyzing and debugging embedded software through dynamic and interactive use of code markers
TL;DR: In this article, a system for inserting code markers for observing indications (external to the microprocessor upon which the software operates) of the occurrence of an event in the execution of the software.
Proceedings ArticleDOI
Operating system support for improving data locality on CC-NUMA compute servers
TL;DR: The experiments show that dynamic page migration and replication can substantially increase application performance, as much as 30%, and reduce contention for resources in the NUMA memory system.
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Apparatus and method for interrupt handling in a multi-threaded operating system kernel
TL;DR: In this paper, a method and apparatus for use in handling interrupts in a data processing system where the kernel is preemptible, has real-time scheduling ability, and which supports multithreading and tightly-coupled multiprocessors is presented.