Patent
Apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
George Z. Chrysos,Jeffrey Dean,James W. Hicks,Daniel L. Leibholz,Edward J. Mclellan,Carl A. Waldspurger,William E. Weihl +6 more
Reads0
Chats0
TLDR
In this article, an apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system, where state information of the system is sampled while any of the selected instructions are in any stage of the pipeline.Abstract:
An apparatus is provided for sampling multiple concurrently executing
instructions in a processor pipeline of a system. The pipeline has a plurality
of processing stages. When the instructions are fetched into a first
stage of the pipeline, the apparatus identifies multiple selected
instructions as a subset of the instructions that one executed
concurrently in the pipeline. State
information of the system is sampled while any of the multiple selected
instructions are in any stage of the pipeline. Software is informed whenever
all of the selected instructions leave the pipeline so that the software can
read any of the state information.read more
References
More filters
Patent
Software performance analyzer
TL;DR: A software performance analyzer nonintrusively measures six different aspects of software execution as mentioned in this paper, including memory activity within a collection of specified address ranges, and the number of transitions between selected pair of programs.
Patent
Instruction sampling instrumentation
TL;DR: In this article, a system and method for instrumenting the execution of instructions in an out-of-sequence execution machine is presented. But it does not address the problem of cache misses or other system conditions.