Patent
Architecture and interconnect scheme for programmable logic circuits
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TLDR
In this paper, a distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs) is presented, where a set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network.Abstract:
An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.read more
Citations
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References
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Patent
Configurable electrical circuit having configurable logic elements and configurable interconnects
TL;DR: In this article, a configurable logic array is defined as a plurality of logic elements that can be configured to perform different logic functions depending upon the control information placed in each logic element.
Patent
Programmable logic array integrated circuits
Richard G. Cliff,L. Todd Cope,Cameron McClintock,William Leong,James A. Watson,Joseph Huang,Bahram Ahanin +6 more
TL;DR: In this article, a programmable logic array integrated circuit (PLLIA) is defined, where the logic array blocks are arranged on the circuit in a two-dimensional array, and a conductor network is provided for interconnecting any logic module with any other logic module, and adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network.
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Programmable interconnect architecture
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TL;DR: An improved programmable logic cell (1) as discussed by the authors is a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b, 8a, 8b) and another to its right (or, to the East) (5a, 5b, 9a, 9b, 10b, 11a, 12b), one above (or below) (2a, 2b, 6a, 6b), and one below (
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