Patent
Architecture for decimation algorithm
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TLDR
In this article, a decimator circuit for implementing a digital algorithm such as a decimation algorithm is described, which is well suited for digital circuits such as delta-sigma (or sigma-delta) analog-to-digital converter.Abstract:
A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.read more
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References
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Analog to digital converter
TL;DR: In this article, the analogue input signal is compared with an electric signal representing the contents of a reversible first counter to control the first counter and also a second counter registering numbers between those registered by the first.
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