Patent
Asynchronous, high-bandwidth memory component using calibrated timing elements
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TLDR
In this paper, an asynchronous memory device that uses internal delay elements to enable memory access pipelining is described. But, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses.Abstract:
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.read more
Citations
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Semiconductor memory device.
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
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Openflow match and action pipeline structure
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TL;DR: In this article, the packet processing pipeline includes match and action stages, each stage in incurs a match delay when match processing occurs and each stage incurs an action delay when action processing occurs.
References
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Patent
Clock vernier adjustment
TL;DR: In this article, a memory system with a memory controller coupled to memory modules through data and command busses is described. But it does not specify the memory controller's role.
Patent
Bus system optimization
Jared L. Zerbe,Kevin S. Donnelly,Stefanos Sidiropoulos,Donald C. Stark,Mark A. Horowitz,Leung Yu,Roxanne Vu,Jun Kim,Bruno W. Garlepp,Tsyr-Chyang Ho,Benedict Lau +10 more
TL;DR: In this article, a bus system comprising a master connected to one or more slaves via a bus is disclosed, which is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device.
Journal ArticleDOI
SLDRAM: high-performance, open-standard memory
P. Gillingham,B. Vogley +1 more
TL;DR: SLDRAM meets the high data bandwidth requirements of emerging processor architectures and retains the low cost of earlier DRAM interface standards, suggesting that SLDRAM will become the mainstream commodity memory of the early 21st century.
Patent
Memory having a plurality of external clock signal inputs
TL;DR: In this paper, a method and apparatus for operating a synchronous memory from a plurality of external clock signals is described, where a memory is operated by delaying operational clock signals such as read and write clock signals, with respect to a system clock signal.
Patent
High speed data transfer synchronizing system and method
TL;DR: In this paper, a memory controller and a plurality of memory modules are connected to a data bus line, clock bus line and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals.